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target data sheet/acdc target specification v 0.7 preliminary 2010-03 microcontrollers 32-bit microcontroller tc1782 32-bit single-chip microcontroller
edition 2010-03 published by infineon technologies ag 81726 munich, germany ? 2010 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, wa rranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
target data sheet/acdc target specification v 0.7 preliminary 2010-03 microcontrollers 32-bit microcontroller tc1782 32-bit single-chip microcontroller
target data sheet/acdc target specif ication i-1 v 0.7 preliminary, 2010-03 tc1782 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1 system overview of the tc1782 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 tc1782 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1 identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.1 parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.2 pad driver and pad classes su mmary . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.2.1 input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.2.2 analog to digital converters (adcx) . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.2.3 fast analog to digital conv erter (fadc) . . . . . . . . . . . . . . . . . . . . . . 1-29 1.2.4 oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 1.2.5 temperature sens or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 1.2.6 power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 1.3 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37 1.3.1 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37 1.3.2 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 1.3.3 power, pad and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 1.3.4 phase locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-42 1.3.5 eray phase locked loop (er ay_pll) . . . . . . . . . . . . . . . . . . . . . . 1-44 1.3.6 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45 1.3.7 dap interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-47 1.3.8 peripheral timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-49 1.3.8.1 micro link interface (mli ) timing . . . . . . . . . . . . . . . . . . . . . . . . . 1-49 1.3.8.2 micro second channel (msc) interface timi ng . . . . . . . . . . . . . . 1-51 1.3.8.3 ssc master/slave mode ti ming . . . . . . . . . . . . . . . . . . . . . . . . . . 1-53 1.3.8.4 eray interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 1.4 package and reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 1.4.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 1.4.2 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-58 1.4.3 flash memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-58 1.4.4 quality declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-60 table of contents
target data sheet/acdc target specif ication i-2 v 0.7 preliminary, 2010-03 tc1782 1.5 pin reliability in overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-61 1.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-61 1.5.1.1 pin classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-61 1.5.1.2 external influences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-61 1.5.1.3 general recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62 1.5.2 positive overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-63 1.5.2.1 reliability at ro om temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 1-63 1.5.2.2 reliability at hi gh temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 1-64 1.5.2.3 reliability calculation me thod . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-65 1.5.3 negative overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-67 1.5.3.1 reliability at hi gh temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 1-67 1.5.4 fadc input buffer reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-70 1.5.5 lvds / cmos combo pad reliability . . . . . . . . . . . . . . . . . . . . . . . . 1-70 1.5.6 overload electrical paramete rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-71
tc1782 target data sheet/acdc target specif ication 3 v 0.7 preliminary, 2010-03
tc1782 target data sheet/acdc target specif ication 4 v 0.7 preliminary, 2010-03
tc1782 summary of features target data sheet/acdc target specif ication 1 v 0.7 preliminary, 2010-03 1 summary of features the sak-tc1782-320f180hl has the following features: ? high-performance 32-bit super-scalar tricore v1.3.1 cpu with 4-stage pipeline ? superior real-time performance ? strong bit handling ? fully integrated dsp capabilities ? single precision floating point unit (fpu) ? 180 mhz operation at full temperature range ? 32-bit peripheral control processo r with single cycle instruction (pcp2) ? 16 kbyte parameter memory (pram) ? 32 kbyte code memory (cmem) ? 180 mhz operation at full temperature range ? multiple on-chip memories ? 2.5 mbyte program flash me mory (pflash) with ecc ? 64 kbyte data flash memory (dfl ash) usable for e eprom emulation ? 128 kbyte data memory (ldram) ? instruction cache: up to 16 kbyte (icache, configurable) ? 40 kbyte code scratc hpad memory (spram) ? data cache: up to 4 kb yte (dcache, configurable) ? 8 kbyte overlay memory (ovram) ? 16 kbyte bootrom (brom) ? 16-channel dma controller ? sophisticated inte rrupt system with 2 255 hardware priority arbitration levels serviced by cpu or pcp2 ? high performing on -chip bus structure ? 64-bit local memory buses betw een cpu, flash an d data memory ? 32-bit system peri pheral bus (spb) for on-chip peripheral and functional units ? one bus bridge (lfi bridge) ? versatile on-chi p peripheral units ? two asynchronous/synchronous serial channels (asc) with baud rate generator, parity, framing and ov errun error detection ? three high-speed synchr onous serial channels (s sc) with programmable data length and shift direction ? one serial micro second bus interface (ms c) for serial port expansion to external power devices ? one high-speed micro link interface (mli) for serial inter-processor communication ? one multican module with 3 can nodes and 128 free assignable message objects for high efficien cy data handling via fifo buffering and gateway data transfer (one can node suppor ts ttcan functionality) ? one flexray tm module with 2 channels (e-ray).
tc1782 summary of features target data sheet/acdc target specif ication 2 v 0.7 preliminary, 2010-03 ? one general purpose timer a rray module (gpta) with ad ditional local timer cell array (ltca2) providing a powerful set of digital signal filtering and timer functionality to realiz e autonomous and complex input/output management ? 32 analog input lines for adc ? 2 independent kernel s (adc0 and adc1) ? analog supply voltage range from 3.3 v to 5 v (single supply) ? 4 different fadc input channels ? channels with impedan ce control and overla id with adc1 inputs ? extreme fast conversion, 21 cycles of f fadc clock ? 10-bit a/d conversion (hi gher resolution can be achieved by averaging of consecutive conversions in di gital data reduction filter) ? 86 digital general pur pose i/o lines (g pio), 4 input lines ? digital i/o ports with 3.3 v capability ? on-chip debug support fo r ocds level 1 (cpu, pcp, dma, on chip bus) ? dedicated emulation device chip available (tc1782ed) ? multi-core debugging, real ti me tracing, and calibration ? four/five wire jtag (ieee 1149.1) or tw o wire dap (device acce ss port) interface ? power management system ? clock generation unit with pll
tc1782 summary of features target data sheet/acdc target specif ication 3 v 0.7 preliminary, 2010-03 the SAK-TC1782-256F133HL has the following features: ? high-performance 32-bit super-scalar tricore v1.3.1 cpu with 4-stage pipeline ? superior real-time performance ? strong bit handling ? fully integrated dsp capabilities ? single precision floating point unit (fpu) ? 133 mhz operation at full temperature range ? 32-bit peripheral control processo r with single cycle instruction (pcp2) ? 16 kbyte parameter memory (pram) ? 32 kbyte code memory (cmem) ? 133 mhz operation at full temperature range ? multiple on-chip memories ? 2 mbyte program flash me mory (pflash) with ecc ? 64 kbyte data flash memory (dfl ash) usable for e eprom emulation ? 128 kbyte data memory (ldram) ? instruction cache: up to 16 kbyte (icache, configurable) ? 40 kbyte code scratc hpad memory (spram) ? data cache: up to 4 kb yte (dcache, configurable) ? 8 kbyte overlay memory (ovram) ? 16 kbyte bootrom (brom) ? 16-channel dma controller ? sophisticated inte rrupt system with 2 255 hardware priority arbitration levels serviced by cpu or pcp2 ? high performing on -chip bus structure ? 64-bit local memory buses betw een cpu, flash an d data memory ? 32-bit system peri pheral bus (spb) for on-chip peripheral and functional units ? one bus bridge (lfi bridge) ? versatile on-chi p peripheral units ? two asynchronous/synchronous serial channels (asc) with baud rate generator, parity, framing and ov errun error detection ? three high-speed synchr onous serial channels (s sc) with programmable data length and shift direction ? one serial micro second bus interface (ms c) for serial port expansion to external power devices ? one high-speed micro link interface (mli) for serial inter-processor communication ? one multican module with 3 can nodes and 128 free assignable message objects for high efficien cy data handling via fifo buffering and gateway data transfer (one can node suppor ts ttcan functionality) ? one general purpose timer a rray module (gpta) with ad ditional local timer cell array (ltca2) providing a powerful set of digital signal filtering and timer functionality to realiz e autonomous and complex input/output management
tc1782 summary of features target data sheet/acdc target specif ication 4 v 0.7 preliminary, 2010-03 ? 32 analog input lines for adc ? 2 independent kernel s (adc0 and adc1) ? analog supply voltage range from 3.3 v to 5 v (single supply) ? 4 different fadc input channels ? channels with impedan ce control and overla id with adc1 inputs ? extreme fast conversion, 21 cycles of f fadc clock ? 10-bit a/d conversion (hi gher resolution can be achieved by averaging of consecutive conversions in di gital data reduction filter) ? 86 digital general pur pose i/o lines (g pio), 4 input lines ? digital i/o ports with 3.3 v capability ? on-chip debug support fo r ocds level 1 (cpu, pcp, dma, on chip bus) ? dedicated emulation device chip available (tc1782ed) ? multi-core debugging, real ti me tracing, and calibration ? four/five wire jtag (ieee 1149.1) or tw o wire dap (device acce ss port) interface ? power management system ? clock generation unit with pll
tc1782 summary of features target data sheet/acdc target specif ication 5 v 0.7 preliminary, 2010-03 ordering information the ordering code for infin eon microcontrollers provides an exact refe rence to the required product. this or dering code identifies: ? the derivative itself, i.e. its function set, the temper ature range, and the supply voltage ? the package and the type of delivery. for the available ordering codes for the tc1782 please refer to the ?product catalog microcontrollers? , which summarizes all avail able microcontroller variants. this document describes the der ivatives of the device.the table 1 enumerates these derivatives and summariz es the differences. table 1 tc1782 derivative synopsis derivative ambient temperature range sak-tc1782-320f180hl t a = -40 o c to +125 o c SAK-TC1782-256F133HL t a = -40 o c to +125 o c
tc1782 system overview of the tc1782 target data sheet/acdc target specif ication 1 v 0.7 preliminary, 2010-03 1 system overview of the tc1782 the tc1782 combines three powerful technologies within one silicon die, achieving new levels of power, sp eed, and economy for embedded applications: ? reduced instruction set computin g (risc) processor architecture ? digital signal processing (d sp) operations a nd addressing modes ? on-chip memories and peripherals dsp operations and addressi ng modes provide the comput ational power necessary to efficiently analyze complex real-world signals. the ri sc load/store architecture provides high computatio nal bandwidth with low system cost. on-chip memory and peripherals are designed to support even the most dem anding high-bandwidth real-time embedded control-systems tasks. additional high-level features of the tc1782 include: ? efficient memory organization: instru ction and data scratch memories, caches ? serial communication interfaces ? fl exible synchronous and asynchronous modes ? peripheral control processo r ? standalone data operations and inte rrupt servicing ? dma controller ? dma opera tions and interrupt servicing ? general-purpose timers ? high-performance on-chip buses ? on-chip debugging and emulation facilities ? flexible interconnections to external components ? flexible power-management the tc1782 is a high-performance microcont roller with tricore cp u, program and data memories, buses, bus arbitration, an interrupt controller, a periphe ral control processor and a dma controller and several on-chip peripherals. the tc1782 is designed to meet the needs of the mo st demanding embedded control systems applications where the competing issues of price/performance, r eal-time responsiveness, computational power, data bandwidth, and power consum ption are key design elements. the tc1782 offers several versatile on-chip pe ripheral units such as serial controllers, timer units, and analog-to-digital converte rs. within the tc1782 , all these peripheral units are connected to the tricore cpu/system via the fl exible peripheral interconnect (fpi) bus and the local memory bus (lmb). several i/o lin es on the tc1782 ports are reserved for these peripher al units to communicate with the external world.
tc1782 system overview of th e tc1782block diagrams target data sheet/acdc target specif ication 2 v 0.7 preliminary, 2010-03 1.1 block diagrams figure 1 shows the block diagram of the sak-tc1782-320f180hl . figure 1 sak-tc1782-320f180hl block diagram figure 1 shows the block diagram of the SAK-TC1782-256F133HL . e-ray (2 channels) ocds l 1 debug interface/ jtag mli0 memcheck fadc tricore cpu pmi interrupt system fpi-bus interface 16 kb pram pcp2 core 32 kb cmem interrupts system peripheral bus system peripheral bus (spb) ssc0 sbcu bridge smif dmi ldram dcache cps bcu pmu gpta0 multi can (3 nodes, 128 m o) asc0 asc1 msc0 (lvd s ) ssc1 stm scu ports ext. request unit ltca2 2,5 mb pflash 128 kb dflash 8 kb ovram 16 kb brom adc0 adc1 blockdiagram sak-tc1782-320f180hl m m/s 3 . 3 v e x t . f a d c s u p p l y 24 kb spram 16 kb icache (configurable) 124 kb ldram 4 kb dcache (configurable) fpu pll e-ray pll f e-ray f cpu abbreviations : icache: instruction cache dcache data cache spram: scratch-pad ram ldram: local data ram ovram: overlay ram brom: boot rom pflash: program flash dflash: data flash pram: parameter ram in pcp pcode: code ram in pcp dma 16 channels 28 (3.3v max) (5v max) 4 4 ssc2 5 v ( 3 . 3 v s u p p o r t e d a s w e l l ) e x t . a d c s u p p l y local memory bus (lmb)
tc1782 system overview of th e tc1782block diagrams target data sheet/acdc target specif ication 3 v 0.7 preliminary, 2010-03 figure 2 SAK-TC1782-256F133HL block diagram ocds l1 debug interface / jtag mli0 memcheck fadc tricore cpu pmi interrupt system fpi-bus interface 16 kb pram pcp2 core 32 kb cmem interrupts system peripheral bus system peripheral bus (spb) ssc0 sbcu bridge smif dmi ldram dcache cps bcu pmu gpta0 multi can (3 nodes, 128 mo) asc0 asc1 msc0 (lvd s ) ssc1 stm scu ports ext. request unit ltca2 2 mb pflash 64 kb dflash 8 kb ovram 16 kb brom adc0 adc1 blockdiagram sak-tc1782- 256f133hl m m/s 3 . 3 v e x t . f a d c s u p p l y 24 kb spram 16 kb icache (configurable) 124 kb ldram 4 kb dcache (configurable) fpu pll e-ray pll f e-ray f cpu abbreviations : icache: instruction cache dcache data cache spram: scratch-pad ram ldram: local data ram ovram: overlay ram brom: boot rom pflash: program flash dflash: data flash pram: parameter ram in pcp pcode: code ram in pcp dma 16 channels 28 (3.3v max) (5v max) 4 4 ssc2 5 v ( 3 . 3 v s u p p o r t e d a s w e l l ) e x t . a d c s u p p l y local memory bus (lmb)
tc1782 pinning target data sheet/acdc target specif ication 1 v 0.7 preliminary, 2010-03 1 pinning figure 1 is showing the tc1782 logic symbol. figure 1 tc1782 logic symbol testmode esr0 porst digital circuitry power supply general control an[35:0] analog inputs v ddm v ssm v ddmf v ssmf v ddaf v ar ef0 v agn d 0 v faref v fagnd v ddfl3 analog power supply tc 1782_lqfp-176-6 v ddosc3 alternate functions oscillator gpta, s cu, e- ray, msc0 gpta, ssc0/1, mli 0, msc0 gpta, asc0/1, ssc0/1, scu, can, msc0 gpta, scu, can v ddosc gpta, mli0, e-ray, ssc2 v ssosc tc1782 port 0 16 port 1 16 port 2 14 port 3 16 port 4 4 port 5 16 port 6 4 gpta, msc0 xtal2 xtal1 v ss 11 v ddp 10 v dd 9 esr1 trst tck / dap0 tdi / brkin tdo / dap2 / brkout tms / dap1 ocds / jtag control gpta, ssc1, adc0, ocds 1) 1) 1 ) only available for sak -tc1782 -320 f180 hl
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 2 v 0.7 preliminary, 2010-03 1.1 tc1782 pin configuration this chapter shows the pi n configuration of the tc 1782 package pg-lqfp-176-6. figure 2 sak-tc1782-320f180hl pinning 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 39 40 41 42 43 44 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 30 31 32 33 34 35 36 37 38 45 46 47 48 49 50 51 52 53 97 96 95 94 93 92 91 90 89 100 99 98 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 13 3 13 4 13 5 13 6 137 13 8 13 9 14 0 14 1 14 2 14 3 14 4 14 5 14 6 147 14 8 14 9 15 0 15 1 15 2 153 154 155 156 157 158 159 160 161 162 16 3 16 4 16 5 16 6 167 16 8 16 9 17 0 17 1 17 2 17 3 17 4 17 5 17 6 p 0.0 /in0 /hw cf g0/o ut0 /out 56 p 0.1 /in1 /hw cf g1/o ut1 /out 57 /s di1 p 0.2 /in2 /hw cf g2/o ut2 /out 58 p 0.3 /in3 /hw cf g3/o ut3 /out 59 p 0.4 /in4 /hw cf g4/o ut4 /out 60 p 0.5 /in5 /hw cf g5/o ut5 /out 61 p 0.6 /in6 /hw cf g6/re q 2/o ut6 /out 62 p 0.7 /in7 /hw cf g7/re q 3/o ut7 /out 63 p 0.8 /in8 /rx da 0/ou t8/ out 64 p 0.9 /in9 /rx db 0/ou t9/ out 65 p 0.1 0/in 10/o ut1 0/t x da 0 p 0.1 1/in 11/o ut1 1/t x db 0 p 0.1 2/in 12/o ut1 2/t x e na p 0.1 3/in 13/o ut1 3/t x e nb p 0.1 4/in 14/r eq 4/o u t1 4/f c lp 0c p 0.1 5/in 15/r eq 5/o ut1 5/s op 0 c p1.0 /in16 /out16 /out72 /brkin/brkout p1.15 /brkin/brkout p1.2/in18/out18/out74 p1.3/in19/out19/out75 p1. 4/in20 /emgstop/out20 /out76 p1.5/in21/out21/out77 p1.6/in22/out22/out78 p1.7/in23/out23/out79 p 1. 8/in24 /in 48/ m t s r1b /out 24 /out 48 p 1. 9/in25 /in 49/ m rs t1b /out 25 /out 49 p 1. 10/ in 26 /in50 /ou t 26 /ou t 50 /s ls o17 p 1. 11/ in 27 /in51 /s c lk 1b / out 27/out 51 ad0emux0/ou t1 6/in16/p1 .12 ad0emux1/o ut1 7/in17/p1 .13 ad0emux2/o ut1 8/in18/p1 .14 t clk 0/ ou t 28/ ou t 32/i n32 /p 2.0 slso 13/ slso03 /out33/tready0a/i n33/ p2.1 t v a lid 0 a/ ou t 29/ ou t 34/i n34/ p2 .2 t d a ta 0/ ou t 30/ ou t 35/i n35/ p2 .3 ou t 31 /out 36/ rc lk 0a /i n36/ p2 .4 r re a d y 0a /o u t3 7/ou t1 10/i n37/ p2 .5 o u t3 8/o u t1 11/ r v al id 0a /i n38/ p 2.6 out39/ rdata0a/i n39/ p2.7 p 2.8 /s ls o0 4/s ls o 14/ en 0 0 p 2.9 /s ls o0 5/s ls o 15/ en 0 1 p 2.1 0/in 10/o ut0 /m rst 1a p 2.1 1/in 11/o ut1 /s clk 1 a/ fcl p0 b p 2.1 2/in 12/o ut2 /m ts r1a / so p 0b p 2.1 3/in 13/o ut3 /s ls i1 1/s di0 p 3.0 out 84/ /rx d0a p 3.1 out 85/ /tx d0 p 3. 2/out 86 /s clk 0 p 3. 3/out 87 /m rs t0 p 3. 4/out 88 /m t s r0 p3. 5/slso 00/ slso10 /slso00 &slso10 p3. 6/slso 01/ slso11 /slso01 &slso11 p 3. 7/s ls i01 /out 89 //s ls o 02 /s ls o12 p 3. 8/s ls o 06/ out 90/t x d 1 p 3.9 /out 91 /rx d1a p 3.1 0/o u t9 2/r e q0 p 3.1 1/o u t9 3//r e q 1 p 3.1 2/o u t9 4//r x d c a n0 /rx d 0b p 3.1 3/o u t9 5//t x d c a n0/t x d0 p 3.1 4/o u t9 6rx d c a n 1/ rx d 1b /s d i2 p 3.1 5/o u t9 7/t x d ca n 1/t x d 1 out 52 /ou t 28 /in 52 /in 2 8/r x dc a n 2/ p 4.0 o u t5 3/o u t2 9/in 5 3/i n 29/ tx dc a n 2/ p 4.1 e x t c lk 1/o ut5 4/o u t3 0/in 54/i n30/ p 4.2 p4. 3/in31 /in 55/ out 31/ out 55/ext clk0 s ls co20 /out 40 /out 8 /in40 /in26 /p 5. 0 s ls co21 /out 41 /out 9 /in41 /in27 /p 5. 1 s ls co22 /out 42 /out 10 /in42 /in28 /p 5. 2 s ls co24 /out 44 /out 12 /in44 /in29 /p 5. 4 s ls co23 /out 43 /out 11 /in43 /p 5. 3 m rs t 2a /ou t 45 /ou t 13 /in45 /in 30 /p 5. 5 m t s r2 a /out 46 /out 14 /in46 /in31 /p 5. 6 s clk 2/out 47 /out 15 /in47 /p 5. 7 rx db 1/ t clk 0/out 95 /p 5.15 t x db 1/rv a lid 0b /out 90 /p 5. 9 txena/ rready0 b/out91/p5.10 t x e nb/rc lk 0 b /out 92 /p 5.11 tdata0/slso07/out93/p5.12 tvalid0b/slso 16 /p5.13 rxda1/t ready0 b/out 94 /p5.14 t xda1 /rdat a0 b/out 89 /p5.8 p 6.1 /in1 5/out 5/ out 81/ fcl p0 a p 6.0 /in1 4/out 4/ out 80/ fcl n0 p 6.3 /in2 5/out 7/ out 83/ so p 0a p 6.2 /in2 4/out 6/ out 82/ so n0 an0 an1 an2 an3 an4 an5 an6 an8 an7 an9 an10 an11 an12 an13 an14 an15 an16 an17 an18 an19 an20 an21 an22 an23 an24 an25 an26 an27 an28 an29 an30 an31 an32 an33 an34 an35 trst p 1.1 /in17 /out 17 /out 73 t di/brkin/ brkout t do/da p 2 /b rk in/b rk out tms/dap1 tck/dap0 esr1 porst v ss testmode xtal1 xtal2 v dd v ddp v ss v dd v dd(sb) tc1782 v dd v ddp v ss v ddmf v ssmf v ddaf v ss v faref v fagnd v ddm v ssm v a ref0 v agnd0 v dd v ddp v ss v dd v ddp v ss v ss v dd v ddp v ss v ddosc v ddosc3 v ssosc v ddf l3 v ddp v ss v dd v ddp v ss v dd(sb ) v ddp v ss sak_tc1782-320f180hl v ddp v ddp esr0
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 3 v 0.7 preliminary, 2010-03 figure 3 SAK-TC1782-256F133HL pinning table 1 pin definitions and func tions (pg-lqfp-176-6 package) pin symbol ctrl. type function port 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 39 40 41 42 43 44 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 30 31 32 33 34 35 36 37 38 45 46 47 48 49 50 51 52 53 97 96 95 94 93 92 91 90 89 100 99 98 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 13 3 13 4 13 5 13 6 137 13 8 13 9 14 0 14 1 14 2 14 3 14 4 14 5 14 6 147 14 8 14 9 15 0 15 1 15 2 153 154 155 156 157 158 159 160 161 162 16 3 16 4 16 5 16 6 167 16 8 16 9 17 0 17 1 17 2 17 3 17 4 17 5 17 6 p 0.0 /in0 /hw cf g0/o ut0 /out 56 p 0.1 /in1 /hw cf g1/o ut1 /out 57 /s di1 p 0.2 /in2 /hw cf g2/o ut2 /out 58 p 0.3 /in3 /hw cf g3/o ut3 /out 59 p 0.4 /in4 /hw cf g4/o ut4 /out 60 p 0.5 /in5 /hw cf g5/o ut5 /out 61 p 0.6 /in6 /hw cf g6/re q 2/o ut6 /out 62 p 0.7 /in7 /hw cf g7/re q 3/o ut7 /out 63 p 0.8 /in8 /out 8/o ut6 4 p 0.9 /in9 /out 9/o ut6 5 p 0.1 0/in 10/o ut1 0 p 0.1 1/in 11/o ut1 1 p 0.1 2/in 12/o ut1 2 p 0.1 3/in 13/o ut1 3 p 0.1 4/in 14/r eq 4/o ut1 4/f clp 0c p 0.1 5/in 15/r eq 5/o ut1 5/s op 0 c p1.0 /in16 /out 16 /out 72 /brk in/b rk out p1.15 /brkin/brkout p1. 2/in18 /out 18 /out 74 p1. 3/in19 /out 19 /out 75 p1. 4/in20 /e m gs t op /out 20 /out 76 p1. 5/in21 /out 21 /out 77 p1. 6/in22 /out 22 /out 78 p1. 7/in23 /out 23 /out 79 p1. 8/in24 /in 48/ m t sr1b /out 24 /out 48 p1. 9/in25 /in 49/ m rst1b /out 25 /out 49 p 1. 10/ in26 /in50 /out 26 /out 50 /s ls o17 p 1. 11/ in27 /in51 /s clk 1b / out 27/out 51 ad0emux0/ou t1 6/in1 6/p1 .12 ad0emux1/o ut1 7/in1 7/p1 .13 ad0emux2/o ut1 8/in1 8/p1 .14 tclk0/out28/out32/in32/p2.0 slso13/slso03/out33/tready0a/in33/p2.1 t valid0 a/ out 29/ out 34/i n34/ p2 .2 t data0/ out 30/ out 35/i n35/ p2 .3 out 31 /out 36/ rclk 0a /i n36/ p2 .4 rready0a/o ut3 7/ou t1 10/i n37/ p2 .5 out38/out111/rvalid0a/in38/p2.6 out 39/ rdata0a/i n39/ p2.7 p2.8 /slso0 4/slso 14/ en0 0 p2.9 /slso0 5/slso 15/ en0 1 p 2.1 0/in 10/o ut0 /m rst 1a p 2.1 1/in 11/o ut1 /s clk 1 a/ fcl p0 b p 2.1 2/in 12/o ut2 /m ts r1a / so p 0b p 2.1 3/in 13/o ut3 /s ls i1 1/s di0 p 3.0 out 84/ /rx d0a p 3.1 out 85/ /tx d0 p3. 2/out 86 /sclk 0 p3. 3/out 87 /m rs t0 p3. 4/out 88 /m t s r0 p3. 5/slso 00/ slso10 /slso00 &slso10 p3. 6/slso 01/ slso11 /slso01 &slso11 p3. 7/s ls i01 /out 89 //s ls o 02 /s lso12 p 3. 8/s ls o 06/ out 90/t x d1 p 3.9 /out 91 /rx d1a p 3.1 0/o ut9 2/re q0 p 3.1 1/o ut9 3//re q 1 p 3.1 2/o ut9 4//rx dca n0 /rx d0b p 3.1 3/o ut9 5//t x dca n0/t x d0 p3.1 4/o ut9 6rxdcan1/ rxd1b/sdi2 p3.1 5/o ut9 7/t xdcan1/t xd1 out 52 /out 28 /in52 /in2 8/rxdcan2/ p4.0 o u t5 3/o u t2 9/in 5 3/i n 29/ tx d c a n 2/ p 4.1 ext clk1/o ut5 4/o ut3 0/in 54/i n30/ p4.2 p 4. 3/in31 /in 55/ out 31/ out 55/e x t clk 0 sls co20 /out 40 /out 8 /in40 /in26 /p 5. 0 sls co21 /out 41 /out 9 /in41 /in27 /p 5. 1 s ls co22 /out 42 /out 10 /in42 /in28 /p 5. 2 s ls co24 /out 44 /out 12 /in44 /in29 /p 5. 4 s lsco23 /out 43 /out 11 /in43 /p 5. 3 m rs t 2a/out 45 /out 13 /in45 /in30 /p 5. 5 m t s r2 a/out 46 /out 14 /in46 /in31 /p 5. 6 s clk 2/out 47 /out 15 /in47 /p 5. 7 t clk 0/out 95 /p 5.15 rv alid 0b/out 90 /p 5. 9 rready0 b/out91/p5.10 rclk0 b/out92/p5.11 tdata0/slso07/out93/p5.12 t v a lid0b /s ls o 16 /p 5.13 tready0 b/out94/p5.14 rdat a0 b/out 89 /p5.8 p6.1 /in1 5/out 5/ out 81/ fcl p0 a p6.0 /in1 4/out 4/ out 80/ fcl n0 p 6.3 /in2 5/out 7/ out 83/ so p 0a p 6.2 /in2 4/out 6/ out 82/ so n0 an0 an1 an2 an3 an4 an5 an6 an8 an7 an9 an10 an11 an12 an13 an14 an15 an16 an17 an18 an19 an20 an21 an22 an23 an24 an25 an26 an27 an28 an29 an30 an31 an32 an33 an34 an35 trst p1.1 /in17 /out 17 /out 73 t di/b rkin/ b rk out t do/dap 2 /b rk in/brk out tms/dap1 tck/dap0 esr1 porst v ss testmode xtal1 xtal2 v dd v ddp v ss v dd v dd(sb) tc1782 v dd v ddp v ss v ddmf v ssmf v ddaf v ss v faref v fagnd v ddm v ssm v a ref 0 v agnd0 v dd v ddp v ss v dd v ddp v ss v ss v dd v ddp v ss v ddosc v ddosc3 v ssosc v ddf l3 v ddp v ss v dd v ddp v ss v dd(sb ) v ddp v ss sak_tc1782-256f133hl v ddp v ddp esr0
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 4 v 0.7 preliminary, 2010-03 145 p0.0 i/o0 a1/ pu port 0 general pu rpose i/o line 0 in0 i gpta0 input 0 in0 i ltca2 input 0 hwcfg0 i hardware configuration input 0 out0 o1 gpta0 output 0 out56 o2 gpta0 output 56 out0 o3 ltca2 output 0 146 p0.1 i/o0 a1/ pu port 0 general pu rpose i/o line 1 in1 i gpta0 input 1 in1 i ltca2 input 1 sdi1 i msc0 serial data input 1 hwcfg1 i hardware configuration input 1 out1 o1 gpta0 output 1 out57 o2 gpta0 output 57 out1 o3 ltca2 output 1 147 p0.2 i/o0 a1/ pu port 0 general pu rpose i/o line 2 in2 i gpta0 input 2 in2 i ltca2 input 2 hwcfg2 i hardware configuration input 2 out2 o1 gpta0 output 2 out58 o2 gpta0 output 58 out2 o3 ltca2 output 2 148 p0.3 i/o0 a+1/ pu port 0 general pu rpose i/o line 3 in3 i gpta0 input 3 in3 i ltca2 input 3 hwcfg3 i hardware configuration input 3 out3 o1 gpta0 output 3 out59 o2 gpta0 output 59 out3 o3 ltca2 output 3 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 5 v 0.7 preliminary, 2010-03 166 p0.4 i/o0 a1/ pu port 0 general pu rpose i/o line 4 in4 i gpta0 input 4 in4 i ltca2 input 4 hwcfg4 i hardware configuration input 4 out4 o1 gpta0 output 4 out60 o2 gpta0 output 60 out4 o3 ltca2 output 4 167 p0.5 i/o0 a1/ pu port 0 general pu rpose i/o line 5 in5 i gpta0 input 5 in5 i ltca2 input 5 hwcfg5 i hardware configuration input 5 out5 o1 gpta0 output 5 out61 o2 gpta0 output 61 out5 o3 ltca2 output 5 173 p0.6 i/o0 a1/ pu port 0 general pu rpose i/o line 6 in6 i gpta0 input 6 in6 i ltca2 input 6 hwcfg6 i hardware configuration input 6 req2 i external request input 2 out6 o1 gpta0 output 6 out62 o2 gpta0 output 62 out6 o3 ltca2 output 6 174 p0.7 i/o0 a1/ pu port 0 general pu rpose i/o line 7 in7 i gpta0 input 7 in7 i ltca2 input 7 hwcfg7 i hardware configuration input 7 req3 i external request input 3 out7 o1 gpta0 output 7 out63 o2 gpta0 output 63 out7 o3 ltca2 output 7 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 6 v 0.7 preliminary, 2010-03 149 p0.8 i/o0 a1/ pu port 0 general pu rpose i/o line 8 in8 i gpta0 input 8 in8 i ltca2 input 8 rxda0 i e-ray channel a recei ve data input 0 1) out8 o1 gpta0 output 8 out64 o2 gpta0 output 64 out8 o3 ltca2 output 8 150 p0.9 i/o0 a1/ pu port 0 general pu rpose i/o line 9 in9 i gpta0 input 9 in9 i ltca2 input 9 rxdb0 i e-ray channel b recei ve data input 0 1) out9 o1 gpta0 output 9 out65 o2 gpta0 output 65 out9 o3 ltca2 output 9 151 p0.10 i/o0 a2/ pu port 0 general pu rpose i/o line 10 in10 i gpta0 input 10 out10 o1 gpta0 output 10 txda0 o2 e-ray channel a tran smit data output 1) out10 o3 ltca2 output 10 152 p0.11 i/o0 a2/ pu port 0 general pu rpose i/o line 11 in11 i gpta0 input 11 out11 o1 gpta0 output 11 txdb0 o2 e-ray channel b tran smit data output 1) out11 o3 ltca2 output 11 168 p0.12 i/o0 a2/ pu port 0 general pu rpose i/o line 12 in12 i gpta0 input 12 out12 o1 gpta0 output 12 txena o2 e-ray channel a transmit data output enable 1) out12 o3 ltca2 output 12 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 7 v 0.7 preliminary, 2010-03 169 p0.13 i/o0 a2/ pu port 0 general pu rpose i/o line 13 in13 i gpta0 input 13 out13 o1 gpta0 output 13 txenb o2 e-ray channel b transmit data output enable 1) out13 o3 ltca2 output 13 175 p0.14 i/o0 a1+/ pu port 0 general pu rpose i/o line 14 in14 i gpta0 input 14 req4 i external request input 4 out14 o1 gpta0 output 14 fclp0c o2 msc0 clock output positive c out14 o3 ltca2 output 14 176 p0.15 i/o0 a1+/ pu port 0 general pu rpose i/o line 15 in15 i gpta0 input 15 req5 i external request input 5 out15 o1 gpta0 output 15 sop0c o2 msc0 serial data output positive c out15 o3 ltca2 output 15 port 1 116 p1.0 i/o0 a2/ pu port 1 general pu rpose i/o line 0 in16 i gpta0 input 16 brkin i break input out16 o1 gpta0 output 16 out72 o2 gpta0 output 72 out16 o3 ltca2 output 16 brkout o break output (controlled by ocds module) 119 p1.1 i/o0 a1/ pu port 1 general pu rpose i/o line 1 in17 i gpta0 input 17 out17 o1 gpta0 output 17 out73 o2 gpta0 output 73 out17 o3 ltca2 output 17 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 8 v 0.7 preliminary, 2010-03 93 p1.2 i/o0 a1/ pu port 1 general pu rpose i/o line 2 in18 i gpta0 input 18 out18 o1 gpta0 output 18 out74 o2 gpta0 output 74 out18 o3 ltca2 output 18 98 p1.3 i/o0 a1/ pu port 1 general pu rpose i/o line 3 in19 i gpta0 input 19 in19 i ltca2 input 19 out19 o1 gpta0 output 19 out75 o2 gpta0 output 75 out19 o3 ltca2 output 19 107 p1.4 i/o0 a1/ pu port 1 general pu rpose i/o line 4 in20 i gpta0 input 20 in20 i ltca2 input 20 emgstop i emergency stop input out20 o1 gpta0 output 20 out76 o2 gpta0 output 76 out20 o3 ltca2 output 20 108 p1.5 i/o0 a1/ pu port 1 general pu rpose i/o line 35 in21 i gpta0 input 21 in21 i ltca2 input 21 out21 o1 gpta0 output 21 out77 o2 gpta0 output 77 out21 o3 ltca2 output 21 109 p1.6 i/o0 a1/ pu port 1 general pu rpose i/o line 6 in22 i gpta0 input 22 in22 i ltca2 input 22 out22 o1 gpta0 output 22 out78 o2 gpta0 output 78 out22 o3 ltca2 output 22 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 9 v 0.7 preliminary, 2010-03 110 p1.7 i/o0 a1/ pu port 1 general pu rpose i/o line 7 in23 i gpta0 input 23 in23 i ltca2 input 23 out23 o1 gpta0 output 23 out79 o2 gpta0 output 79 out23 o3 ltca2 output 23 94 p1.8 i/o0 a1+/ pu port 1 general pu rpose i/o line 8 in24 i gpta0 input 24 in48 i gpta0 input 48 mtsr1b i ssc1 slave receive input b (slave mode) out24 o1 gpta0 output 24 out48 o2 gpta0 output 48 mtsr1b o3 ssc1 master transmit output b (master mode) 95 p1.9 i/o0 a1+/ pu port 1 general pu rpose i/o line 9 in25 i gpta0 input 25 in49 i gpta0 input 49 mrst1b i ssc1 master receive in put b (master mode) out25 o1 gpta0 output 25 out49 o2 gpta0 output 49 mrst1b o3 ssc1 slave transmit output b (slave mode) 96 p1.10 i/o0 a1+/ pu port 1 general pu rpose i/o line 10 in26 i gpta0 input 26 in50 i gpta0 input 50 out26 o1 gpta0 output 26 out50 o2 gpta0 output 50 slso17 o3 ssc1 slave select output 7 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 10 v 0.7 preliminary, 2010-03 97 p1.11 i/o0 a1+/ pu port 1 general pu rpose i/o line 11 in27 i gpta0 input 27 in51 i gpta0 input 51 sclk1b i ssc1 clock input b out27 o1 gpta0 output 27 out51 o2 gpta0 output 51 sclk1b o3 ssc1 clock output b 73 p1.12 i/o0 a1/ pu port 1 general pu rpose i/o line 12 in16 i ltca2 input 16 ad0emux0 o1 adc0 external multipl exer control output 0 ad0emux0 o2 adc0 external multipl exer control output 0 out16 o3 ltca2 output 16 72 p1.13 i/o0 a1/ pu port 1 general pu rpose i/o line 13 in17 i ltca2 input 17 ad0emux1 o1 adc0 external multipl exer control output 1 ad0emux1 o2 adc0 external multipl exer control output 1 out17 o3 ltca2 output 17 71 p1.14 i/o0 a1/ pu port 1 general pu rpose i/o line 14 in18 i ltca2 input 18 ad0emux2 o1 adc0 external multipl exer control output 2 ad0emux2 o2 adc0 external multipl exer control output 2 out18 o3 ltca2 output 18 117 p1.15 i/o0 a2/ pu port 1 general pu rpose i/o line 15 brkin i break input reserved o1 - reserved o2 - reserved o3 - brkout o break output (controlled by ocds module) port 2 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 11 v 0.7 preliminary, 2010-03 74 p2.0 i/o0 a2/ pu port 2 general pu rpose i/o line 0 in32 i gpta0 input 32 out32 o1 gpta0 output 32 tclk0 o2 mli0 transmitter clock output 0 out28 o3 ltca2 output 28 75 p2.1 i/o0 a2/ pu port 2 general pu rpose i/o line 1 in33 i gpta0 input 33 tready0a i mli0 transmitte r ready input a out33 o1 gpta0 output 33 slso03 o2 ssc0 slave select output line 3 slso13 o3 ssc1 slave select output line 3 76 p2.2 i/o0 a2/ pu port 2 general pu rpose i/o line 2 in34 i gpta0 input 34 out34 o1 gpta0 output 34 tvalid0 o2 mli0 transmitter valid output out29 o3 ltca2 output 29 77 p2.3 i/o0 a2/ pu port 2 general pu rpose i/o line 3 in35 i gpta0 input 35 out35 o1 gpta0 output 35 tdata0 o2 mli0 transmitter data output out30 o3 ltca2 output 30 78 p2.4 i/o0 a2/ pu port 2 general pu rpose i/o line 4 in36 i gpta0 input 36 rclk0a i mli receiver clock input a out36 o1 gpta0 output 36 out36 o2 gpta0 output 36 out31 o3 ltca2 output 31 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 12 v 0.7 preliminary, 2010-03 79 p2.5 i/o0 a2/ pu port 2 general pu rpose i/o line 5 in37 i gpta0 input 37 out37 o1 gpta0 output 37 rready0a o2 mli0 receiver ready output a out110 o3 ltca2 output 110 80 p2.6 i/o0 a2/ pu port 2 general pu rpose i/o line 6 in38 i gpta0 input 38 rvalid0a i mli receiver valid input a out38 o1 gpta0 output 38 out38 o2 gpta0 output 38 out111 o3 ltca2 output 111 81 p2.7 i/o0 a2/ pu port 2 general pu rpose i/o line 7 in39 i gpta0 input 39 rdata0a i mli receiver data input a out39 o1 gpta0 output 39 out39 o2 gpta0 output 39 reserved o3 - 164 p2.8 i/o0 a2/ pu port 2 general pu rpose i/o line 8 slso04 o1 ssc0 slave select output 4 slso14 o2 ssc1 slave select output 4 en00 o3 msc0 enable output 0 160 p2.9 i/o0 a2/ pu port 2 general pu rpose i/o line 9 slso05 o1 ssc0 slave select output 5 slso15 o2 ssc1 slave select output 5 en01 o3 msc0 enable output 1 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 13 v 0.7 preliminary, 2010-03 161 p2.10 i/o0 a1+/ pu port 2 general pu rpose i/o line 10 mrst1a i ssc1 master receive input a in10 i ltca2 input 10 mrst1a o1 ssc1 slave transmit output out0 o2 ltca2 output 0 reserved o3 - 162 p2.11 i/o0 a1+/ pu port 2 general pu rpose i/o line 11 sclk1a i ssc1 clock input a in11 i ltca2 input 11 sclk1a o1 ssc1 clock output a out1 o2 ltca2 output 1 fclp0b o3 msc0 clock output positive b 163 p2.12 i/o0 a1+/ pu port 2 general pu rpose i/o line 12 mtsr1a i ssc1 slave receive input a in12 i ltca2 input 12 mtsr1a o1 ssc1 master transmit output a out2 o2 ltca2 output 2 sop0b o3 msc0 serial data output positive b 165 p2.13 i/o0 a1/ pu port 2 general pu rpose i/o line 13 slsi11 i ssc1 slave sele ct input 1 sdi0 i msc0 serial data input 0 in13 i ltca2 input 13 out3 o1 ltca2 output 3 reserved o2 - reserved o3 - port 3 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 14 v 0.7 preliminary, 2010-03 136 p3.0 i/o0 a1+/ pu port 3 general pu rpose i/o line 0 rxd0a i asc0 receiver input a (async. & sync. mode) rxd0a o1 asc0 output (sync. mode) rxd0a o2 asc0 output (sync. mode) out84 o3 gpta0 output 84 135 p3.1 i/o0 a1+/ pu port 3 general pu rpose i/o line 1 txd0 o1 asc0 output txd0 o2 asc0 output out85 o3 gpta0 output 85 129 p3.2 i/o0 a1+/ pu port 3 general pu rpose i/o line 2 sclk0 i ssc0 clock input (slave mode) sclk0 o1 ssc0 clock output (master mode) sclk0 o2 ssc0 clock output (master mode) out86 o3 gpta0 output 86 130 p3.3 i/o0 a1+/ pu port 3 general pu rpose i/o line 3 mrst0 i ssc0 master receive input (master mode) mrst0 o1 ssc0 slave transmit output (slave mode) mrst0 o2 ssc0 slave transmit output (slave mode) out87 o3 gpta0 output 87 132 p3.4 i/o0 a2/ pu port 3 general pu rpose i/o line 4 mtsr0 i ssc0 slave receive in put (slave mode) mtsr0 o1 ssc0 master transmit output (master mode) mtsr0 o2 ssc0 master transmit output (master mode) out88 o3 gpta0 output 88 126 p3.5 i/o0 a1+/ pu port 3 general pu rpose i/o line 5 slso00 o1 ssc0 slave select output 0 slso10 o2 ssc1 slave select output 0 slsoando0 o3 ssc0 and ssc1 slave select output 0 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 15 v 0.7 preliminary, 2010-03 127 p3.6 i/o0 a1+/ pu port 3 general pu rpose i/o line 6 slso01 o1 ssc0 slave select output 1 slso11 o2 ssc1 slave select output 1 slsoando1 o3 ssc0 and ssc1 slave select output 1 131 p3.7 i/o0 a2/ pu port 3 general pu rpose i/o line 7 slsi01 i ssc0 slave sele ct input 1 slso02 o1 ssc0 slave select output 2 slso12 o2 ssc1 slave select output 2 out89 o3 gpta0 output 89 128 p3.8 i/o0 a2/ pu port 3 general pu rpose i/o line 8 slso06 o1 ssc0 slave select output 6 txd1 o2 asc1 transmit output out90 o3 gpta0 output 90 138 p3.9 i/o0 a1/ pu port 3 general pu rpose i/o line 9 rxd1a i asc1 receiver input a rxd1a o1 asc1 receiver output a (synchronous mode) rxd1a o2 asc1 receiver output a (synchronous mode) out91 o3 gpta0 output 91 137 p3.10 i/o0 a1/ pu port 3 general pu rpose i/o line 10 req0 i external request input 0 reserved o1 - reserved o2 - out92 o3 gpta0 output 92 144 p3.11 i/o0 a1/ pu port 3 general pu rpose i/o line 11 req1 i external request input 1 reserved o1 - reserved o2 - out93 o3 gpta0 output 93 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 16 v 0.7 preliminary, 2010-03 143 p3.12 i/o0 a1/ pu port 3 general pu rpose i/o line 12 rxdcan0 i can node 0 receiver input rxd0b i asc0 receiver input b rxd0b o1 asc0 receiver output b (synchronous mode) rxd0b o2 asc0 receiver output b (synchronous mode) out94 o3 gpta0 output 94 142 p3.13 i/o0 a2/ pu port 3 general pu rpose i/o line 13 txdcan0 o1 can node 0 tran smitter output txd0 o2 asc0 transmit output out95 o3 gpta0 output 95 134 p3.14 i/o0 a1/ pu port 3 general pu rpose i/o line 14 rxdcan1 i can node 1 receiver input rxd1b i asc1 receiver input b sdi2 i msc0 serial data input 2 rxd1b o1 asc1 receiver output b (synchronous mode) rxd1b o2 asc1 receiver output b (synchronous mode) out96 o3 gpta0 output 96 133 p3.15 i/o0 a2/ pu port 3 general pu rpose i/o line 15 txdcan1 o1 can node 1 tran smitter output txd1 o2 asc1 transmit output out97 o3 gpta0 output 97 port 4 86 p4.0 i/o0 a1+/ pu port 4 general pu rpose i/o line 0 in28 i gpta0 input 28 in52 i gpta0 input 52 rxdcan2 i can node 2 receiver input out28 o1 gpta0 output 28 out52 o2 gpta0 output 52 reserved o3 - table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 17 v 0.7 preliminary, 2010-03 87 p4.1 i/o0 a1+/ pu port 4 general pu rpose i/o line 1 in29 i gpta0 input 29 in53 i gpta0 input 53 out29 o1 gpta0 output 29 out53 o2 gpta0 output 53 txdcan2 o3 can node 2 tran smitter output 88 p4.2 i/o0 a2/ pu port 4 general pu rpose i/o line 2 in30 i gpta0 input 30 in54 i gpta0 input 54 out30 o1 gpta0 output 30 out54 o2 gpta0 output 54 extclk1 o3 external clock 1 output 90 p4.3 i/o0 a2/ pu port 4 general pu rpose i/o line 3 in31 i gpta0 input 31 in55 i gpta0 input 55 out31 o1 gpta0 output 31 out55 o2 gpta0 output 55 extclk0 o3 external clock 0 output port 5 1p5.0 i/o0a1+/ pu port 5 general pu rpose i/o line 0 in40 i gpta0 input 40 in26 i ltca2 input 26 out40 o1 gpta0 output 40 out8 o2 ltca2 output 8 slso20 o3 ssc2 slave select output 0 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 18 v 0.7 preliminary, 2010-03 2p5.1 i/o0a1+/ pu port 5 general pu rpose i/o line 1 in41 i gpta0 input 41 in27 i ltca2 input 27 out41 o1 gpta0 output 41 out9 o2 ltca2 output 9 slso21 o3 ssc2 slave select output 1 3p5.2 i/o0a1+/ pu port 5 general pu rpose i/o line 2 in42 i gpta0 input 42 in28 i ltca2 input 28 out42 o1 gpta0 output 42 out10 o2 ltca2 output 10 slso22 o3 ssc2 slave select output 2 4p5.3 i/o0a1+/ pu port 5 general pu rpose i/o line 3 in43 i gpta0 input 43 out43 o1 gpta0 output 43 out11 o2 ltca2 output 11 slso23 o3 ssc2 slave select output 3 5p5.4 i/o0a1+/ pu port 5 general pu rpose i/o line 4 in44 i gpta0 input 44 in29 i ltca2 input 29 slsi2a i ssc2 slave sele ct input a out44 o1 gpta0 output 44 out12 o2 ltca2 output 12 slso24 o3 ssc2 slave select output 4 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 19 v 0.7 preliminary, 2010-03 6p5.5 i/o0a1+/ pu port 5 general pu rpose i/o line 5 in45 i gpta0 input 45 in30 i ltca2 input 30 mrst2a i ssc2 master receive input (master mode) out45 o1 gpta0 output 45 out13 o2 ltca2 output 13 mrst2 o3 ssc2 master transmit input (slave mode) 7p5.6 i/o0a1+/ pu port 5 general pu rpose i/o line 6 in46 i gpta0 input 46 in31 i ltca2 input 31 mtsr2a i ssc2 slave receive in put (slave mode) out46 o1 gpta0 output 46 out14 o2 ltca2 output 14 mtsr2 o3 ssc2 master transmit output (master mode) 8p5.7 i/o0a1+/ pu port 5 general pu rpose i/o line 7 in47 i gpta0 input 47 sclk2a i ssc2 clock input (slave mode) out47 o1 gpta0 output 47 out15 o2 ltca2 output 15 sclk2 o3 ssc2 clock output (master mode) 13 p5.8 i/o0 a2/ pu port 5 general pu rpose i/o line 8 rdata0b i mli0 receiver data input b reserved o1 - txda1 o2 e-ray channel a tran smit data output 1) out89 o3 ltca2 output 89 14 p5.9 i/o0 a2/ pu port 5 general pu rpose i/o line 9 rvalid0b i mli0 receiver data valid input b reserved o1 - txdb1 o2 e-ray channel b tran smit data output 1) out90 o3 ltca2 output 90 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 20 v 0.7 preliminary, 2010-03 15 p5.10 i/o0 a2/ pu port 5 general pu rpose i/o line 10 rready0b o1 mli0 receiver ready input b txena o2 e-ray channel a transmit data output enable 1) out91 o3 ltca2 output 91 16 p5.11 i/o0 a2/ pu port 5 general pu rpose i/o line 11 rclk0b i mli0 receiver clock input b reserved o1 - txenb o2 e-ray channel b transmit data output enable 1) out92 o3 ltca2 output 92 17 p5.12 i/o0 a1+/ pu port 5 general pu rpose i/o line 12 tdata0 o1 mli0 transmitter data output slso07 o2 ssc0 slave select output 7 out93 o3 ltca2 output 93 18 p5.13 i/o0 a1+/ pu port 5 general pu rpose i/o line 13 tvalid0b o1 mli0 transmitter valid input b slso16 o2 ssc1 slave select output 6 reserved o3 - 19 p5.14 i/o0 a1+/ pu port 5 general pu rpose i/o line 14 tready0b i mli0 transmitte r ready input b rxda1 i e-ray channel a recei ve data input 1 1) reserved o1 - reserved o2 - out94 o3 ltca2 output 94 9 p5.15 i/o0 a1+/ pu port 5 general pu rpose i/o line 15 rxdb1 i e-ray channel b recei ve data input 1 1) tclk0 o1 mli0 transmitter clock output reserved o2 - out95 o3 ltca2 output 95 port 6 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 21 v 0.7 preliminary, 2010-03 156 p6.0 i/o0 a1/ f/ pu port 6 general pu rpose i/o line 0 in14 i ltca2 input 14 fcln0 o1 msc0 clock output negative out80 o2 gpta0 output 80 out4 o3 ltca2 output 4 157 p6.1 i/o0 a1/ f/ pu port 6 general pu rpose i/o line 1 in15 i ltca2 input 15 fclp0a o1 msc0 clock output positive a out81 o2 gpta0 output 81 out5 o3 ltca2 output 5 158 p6.2 i/o0 a1/ f/ pu port 6 general pu rpose i/o line 2 in24 i ltca2 input 24 son0 o1 msc0 serial data output negative out82 o2 gpta0 output 82 out6 o3 ltca2 output 6 159 p6.3 i/o0 a1/ f/ pu port 6 general pu rpose i/o line 3 in25 i ltca2 input 25 sop0a o1 msc0 serial data output positive a out83 o2 gpta0 output 83 out7 o3 ltca2 output 7 analog input port 67 an0 i d analog input 0 66 an1 i d analog input 1 65 an2 i d analog input 2 64 an3 i d analog input 3 63 an4 i d analog input 4 62 an5 i d analog input 5 61 an6 i d analog input 6 36 an7 i d analog input 7 60 an8 i d analog input 8 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 22 v 0.7 preliminary, 2010-03 59 an9 i d analog input 9 58 an10 i d analog input 10 57 an11 i d analog input 11 56 an12 i d analog input 12 55 an13 i d analog input 13 50 an14 i d analog input 14 49 an15 i d analog input 15 48 an16 i d analog input 16 47 an17 i d analog input 17 46 an18 i d analog input 18 45 an19 i d analog input 19 44 an20 i d analog input 20 43 an21 i d analog input 21 42 an22 i d analog input 22 41 an23 i d analog input 23 40 an24 i d analog input 24 39 an25 i d analog input 25 38 an26 i d analog input 26 37 an27 i d analog input 27 35 an28 i d analog input 28 34 an29 i d analog input 29 33 an30 i d analog input 30 32 an31 i d analog input 31 31 an32 i d analog input 32 30 an33 i d analog input 33 29 an34 i d analog input 34 28 an35 i d analog input 35 54 v ddm -- adc analog part powe r supply (3.3v - 5v) 53 v ssm -- adc analog part ground table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 23 v 0.7 preliminary, 2010-03 52 v aref0 -- adc0 reference voltage v aref1 -- adc1 reference voltage 51 v agnd0 -- adc refere nce ground 24 v ddmf -- fadc analog part po wer supply (3.3v) 23 v ddaf -- fadc analog part logic power supply (1.3v) 25 v ssmf -- fadc analog part ground v ssaf -- fadc analog part ground 26 v faref -- fadc reference voltage 27 v fagnd -- fadc reference ground 10, 21 2) , 68, 84, 91, 99, 123, 153, 170 2) v dd -- digital core power supply (1.3v) 11, 20, 69, 83, 89, 100, 124, 139, 154, 171 v ddp -- port power supply (3.3v) table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 24 v 0.7 preliminary, 2010-03 12, 22, 70, 82, 85, 92, 101, 125, 140, 155, 172 v ss -- digital ground 105 v ddosc -- main oscillator and pl l power supply (1.3v) 106 v ddosc3 -- main oscillator power supply (3.3v) 104 v ssosc -- main oscillator and pll ground 141 v ddfl3 -- power supply for flash (3.3v) 102 xtal1 i main oscillator input 103 xtal2 o main oscillator output 111 tdi i a2/ pu jtag serial data input brkin i ocds break input line brkout o ocds break output line 112 tms i a2/ pd jtag state machin e control input dap1 i/o device access port line 1 113 tdo i/o a2/ pu jtag serial data output dap2 i/o device access port line 2 brkin i ocds break input line brkout o ocds break output line 114 trst i i / pd jtag reset input 115 tck i a1/ pd jtag clock input dap0 i device access port line 0 118 testmode i i / pu test mode select input 120 esr1 i/o a2/ pd external system re quest reset input 1 table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 pinningtc1782 pi n configuration target data sheet/acdc target specif ication 25 v 0.7 preliminary, 2010-03 legend for table 1 column ? ctrl. ?: i = input (for gpio port lines with iocr bit field selection pcx = 0xxx b ) o = output o0 = output with iocr bit field selection pcx = 1x00 b o1 = output with iocr bit field selection pcx = 1x01 b (alt1) o2 = output with iocr bit field selection pcx = 1x10 b (alt2) o3 = output with iocr bit fiel d selection pcx = 1x11(alt3) column ? type ?: a1 = pad class a1 (lvttl) a2 = pad class a2 (lvttl) a5 = pad class a5 (lvttl) f = pad class f (lvds/cmos) d = pad class d (adc) pu = with pull-up device conne cted during reset (porst = 0) pd = with pull-down device co nnected during reset (porst = 0) tr = tri-state during reset (porst = 0) 121 porst i i / pd power on reset input 122 esr0 i/o a2 external system re quest reset input 0 default configuration duri ng and after reset is open-drain driver. the driv er drives low during power-on reset. 1) only available for sak-tc1782-320f180hl. 2) for the emulation device (ed), this pin is bonded to vddsb (ed stand by ram supply). in the production devide device, this pin is bonded to a vdd pad. table 1 pin definitions and func tions (pg-lqfp-176-6 package) (cont?d) pin symbol ctrl. type function
tc1782 identification registers target data sheet/acdc target specif ication 1 v 0.7 preliminary, 2010-03 1 identification registers the identification regi sters uniquely identify the whole device. table 1 sak-tc1782-320f180hl identification registers short name value address stepping cbs_jdpid 0000 6350 h f000 0408 h ab cbs_jtagid 1018 e083 h f000 0464 h ab scu_chipid 0500 9301 h f000 0640 h ab scu_manid 0000 1820 h f000 0644 h ab scu_rtid 0000 0002 h f000 0648 h ab table 2 SAK-TC1782-256F133HL identification registers short name value address stepping cbs_jdpid 0000 6350 h f000 0408 h ab cbs_jtagid 1018 e083 h f000 0464 h ab scu_chipid 1400 9301 h f000 0640 h ab scu_manid 0000 1820 h f000 0644 h ab scu_rtid 0000 0002 h f000 0648 h ab
tc1782 electrical parameters general parameters target data sheet/acdc target specif ication 1 v 0.7 preliminary, 2010-03 1 electrical parameters this specification provides all el ectrical parameters of the tc1782. 1.1 general parameters 1.1.1 parameter interpretation the parameters listed in this section partly repr esent the characteri stics of the tc1782 and partly its requirements on the system. to aid interpre ting the parameters easily when evaluating them for a design, they ar e marked with an two- letter abbreviation in column ?symbol?: ? cc such parameters indicate c ontroller c haracteristics which are a distinctive feature of the tc1782 and must be regarded for a system design. ? sr such paramete rs indicate s ystem r equirements which must provided by the microcontroller system in wh ich the tc1782 designed in.
tc1782 electrical parameters general parameters target data sheet/acdc target specif ication 2 v 0.7 preliminary, 2010-03 1.1.2 pad driver and pad classes summary this section gives an overview on the di fferent pad driver cl asses and its basic characteristics. more details (main ly dc parameters) are defined in the section 1.2.1 . table 1 pad driver an d pad classes overview class power supply type sub class speed grade load leakage 150 o c termination a 3.3 v lvttl i/o, lvttl outputs a1 (e.g. gpio) 6mhz 100pf 500na no a1+ (e.g. serial i/os) 25 mhz 50 pf 1 aseries termination recommended a2 (e.g. serial i/os) 40 mhz 50 pf 3 aseries termination recommended f 3.3 v lvds ? 50 mhz ?? parallel termination, 100 10% 1) 1) in applications where the lvds pins are not used (disabled), these pins must be either left unconnected, or properly terminated with the differential parallel termination of 100 10%. cmos ? 6 mhz 50 pf ? d e 5v adc ? ? ? ? i 3.3 v lvttl (input only) ????
tc1782 electrical parameters general parameters target data sheet/acdc target specif ication 3 v 0.7 preliminary, 2010-03 1.1.3 absolute maximum ratings stresses above the values listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditi ons above those indica ted in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions may affect device reliability. table 2 absolute maximu m rating parameters parameter symbol values unit note / test con dition min. typ. max. storage temperature t st sr -65 ? 150 c? voltage at 1.3 v power supply pins with respect to v ss v dd sr ? ? 2.0 v ? voltage at 3.3 v power supply pins with respect to v ss v ddp sr ??4.3 v? voltage at 5 v power supply pins with respect to v ss v ddm sr ? ? 7.0 v ? voltage on any class a input pin and dedicated input pins with respect to v ss v in sr -0.5 ? v ddp + 0.5 or max. 4.3 v whatever is lower voltage on any class d analog input pin with respect to v agnd v ain v arefx sr -0.5 ? 7.0 v ? voltage on any shared class d analog input pin with respect to v ssaf , if the fadc is switched through to the pin. v ainf v faref sr -0.5 ? 7.0 v ?
tc1782 electrical parameters general parameters target data sheet/acdc target specif ication 4 v 0.7 preliminary, 2010-03 1.1.4 operating conditions the following operating conditi ons must not be exceeded in order to ensure correct operation and reliability of t he tc1782. all parameters spec ified in the following tables refer to these operating cond itions, unless otherwise noticed. digital supply voltages appl ied to the tc1782 must be stat ic regulated voltages which allow a typical volt age swing of 5 %. table 3 operating cond itions parameters parameter symbol values unit note / test condition min. typ. max. overload coupling factor for analog inputs, negative k ovan cc ?? 0.0005 i ov 0ma; i ov -1 ma; analog pad= 5.0 v overload coupling factor for analog inputs, positive k ovap cc ?? 0.0000 5 i ov 3ma; i ov 0ma; analog pad= 5.0 v cpu frequency f cpu sr ?? 133 mhz product = sak- tc1782-256f 133hl ?? 180 mhz product = sak- tc1782-320f 180hl fpi bus frequency f fpi sr ?? 90 mhz lmb frequency f lmb cc ?? 133 mhz product = sak- tc1782-256f 133hl ?? 180 mhz product = sak- tc1782-320f 180hl pcp frequency f pcp sr ?? 133 mhz product = sak- tc1782-256f 133hl ?? 180 mhz product = sak- tc1782-320f 180hl
tc1782 electrical parameters general parameters target data sheet/acdc target specif ication 5 v 0.7 preliminary, 2010-03 inactive device pin current i id sr -1 ? 1ma all power supply voltagesv ddx = 0 short circuit current of digital outputs 1) i sc sr -5 ? 5ma absolute sum of short circuit currents of the device 2) i sc_d cc ?? 100 ma absolute sum of short circuit currents per pin group 2) i sc_pg cc ?? 20 ma ambient temperature t a sr -40 ? 125 c junction temperature t j sr -40 ? 150 c core supply voltage v dd sr 1.235 1.3 1.365 3) v flash supply voltage 3.3v v ddfl3 sr 3.13 3.3 3.47 4) v adc analog supply voltage v ddm sr 3.13 3.3 5.5 v oscillator core supply voltage v ddosc sr 1.235 1.3 1.365 3) v oscillator 3.3v supply voltage v ddosc3 sr 3.13 3.3 3.47 4) v digital supply voltage for io pads v ddp sr 3.13 3.3 3.47 4) v vddp voltage to ensure defined pad states 5) v ddppa cc 0.65 ?? v digital ground voltage v ss sr 0 ?? v analog ground voltage for v ddm v ssm sr -0.1 0 0.1 v analog core supply v ddaf sr 1.235 1.3 1.365 3) v table 3 operating cond itions parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parameters general parameters target data sheet/acdc target specif ication 6 v 0.7 preliminary, 2010-03 extended range op erating conditions the following extend ed operating conditions are defined: ?1.3v+5%< v dd / v ddosc / v ddaf <1.3v + 7.5% (overvoltage condition): ? limited to 10000 hour duratio n cumulative in lifetime, due to the reli ability reduction of the chip caused by the overvoltage stress. ? 1.3v + 7.5% < v dd / v ddosc / v ddaf <1.3v + 10% (overvoltage condition): ? limited to 1 hour duration cumulative in lifetime, due to the reliability reduction of the chip caused by th e overvoltage stress. ? v ddp / v ddosc3 / v ddfl3 / v ddmf <3.3v 10% ?3.3v+5%< v ddp / v ddosc3 / v ddfl3 / v ddmf <3.3v + 10% (overvoltage condition): limited to 1 hour duration cumulative in lifetime, due to the reliability reduction of the chip caused by th e overvoltage stress. ? 3.3v - 10% < v ddp / v ddosc3 / v ddfl3 / v ddmf <3.3v ? 5% (undervoltage condition): -reduces gpio pads performance -no program / delete of dflash for t j >125 o c -no program / delete of pflash at all fadc / adc analog supply voltage v ddmf sr 3.13 3.3 3.47 4) v analog ground voltage for v ddmf v ssaf sr -0.1 0 0.1 v 1) applicable for digital outputs. 2) see also section pin reliability in overload for overload currect definitions. 3) voltage overshoot to 1.7v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 4) voltage overshoot to 4.0v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 5) this parameter is valid under the assumption the porst signal is constantly at low level during the power- up/power-down of v ddp . table 3 operating cond itions parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parameters general parameters target data sheet/acdc target specif ication 7 v 0.7 preliminary, 2010-03 table 4 pin groups for overload / sho rt-circuit current sum parameter group pins 1 p5.[7:2], p5.15 2 p5.[9:8] 3 p5.[11:10] 4 p5.[14:12] 5 p1.[14:12], p2.0 6 p2.[4:1] 7 p2.[7:5] 8 p4.[2:0] 9p4.3 10 p1.2, p1.8 11 p1.[10:9] 12 p1.3, p1.11 13 p1.[7:4] 14 p1.[1:0], p1.15 15 p3.[8:5], p3.[3:2] 16 p3.[1:0], p3.4, p3.[10:9], p3.[15:14] 17 p0.[1:0], p3.[13:11] 18 p0.[3:2], p0.[9:8] 19 p0.[11:10] 20 p6.[3:0] 21 p2.[13:8] 22 p0.[5:4], p0.[13:12] 23 p0.[7:6], p0.[15:14], p5.[1:0]
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 8 v 0.7 preliminary, 2010-03 1.2 dc parameters 1.2.1 input/output pins table 5 standard_pads parameters parameter symbol values unit note / test condition min. typ. max. pin capacitance (digital inputs/outputs) c io cc ?? 10 pf t a =25c; f =1mhz pull-down current | i pdl | cc ?? 150 a v i 0.6 x v ddp v 10 ?? a v i 0.36 x v ddp v pull-up current | i puh | cc 10 ?? a v i 0.6 x v ddp v ?? 100 a v i 0.36 x v ddp v spike filter always blocked pulse duration t sf1 cc ?? 10 ns spike filter pass-through pulse duration t sf2 cc 100 ?? ns table 6 standard_pads class_a1 parameter symbol values unit note / test condition min. typ. max. input hysteresis for pads of all a classes 1) hysa cc 0.1 x v ddp ?? v input leakage current class a1 i oza1 cc -500 ? 500 na v i 0v; v i v ddp v ratio vil/vih, a1 pads v ila1 / v iha1 cc 0,6 ??
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 9 v 0.7 preliminary, 2010-03 on-resistance of the a1 pad, medium edge r dson1 cc ?? 140 ohm i oh <2ma; i ol <2ma; p_mos ?? 100 ohm i oh <2ma; i ol <2ma; n_mos fall time,pad type a1 t fa1 cc ?? 150 ns c l = 20 pf; pin out driver= weak ?? 50 ns c l = 50 pf; pin out driver= medium ?? 140 ns c l = 150 pf; pin out driver= medium ?? 550 ns c l = 150 pf; pin out driver= weak ?? 18000 ns c l = 20000 pf; pin out driver= medium ?? 65000 ns c l = 20000 pf; pin out driver= weak table 6 standard_pads class_a1 (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 10 v 0.7 preliminary, 2010-03 rise time, pad type a1 t ra1 cc ?? 150 ns c l = 20 pf; pin out driver= weak ?? 50 ns c l = 50 pf; pin out driver= medium ?? 140 ns c l = 150 pf; pin out driver= medium ?? 550 ns c l = 150 pf; pin out driver= weak ?? 18000 ns c l = 20000 pf; pin out driver= medium ?? 65000 ns c l = 20000 pf; pin out driver= weak input high voltage class a1 pads v iha1 sr 0.6 x v ddp ? min(v ddp + 0.3,3.6 ) v input low voltage class a1 pads v ila1 sr -0.3 ? 0.36 x v ddp v table 6 standard_pads class_a1 (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 11 v 0.7 preliminary, 2010-03 output voltage high class a1 pads v oha1 cc v ddp - 0.4 ?? v i oh -1.4 ma; pin out driver= medium 2.4 ?? v i oh -2 ma; pin out driver= medium v ddp - 0.4 ?? v i oh -400 a; pin out driver= weak 2.4 ?? v i oh -500 a; pin out driver= weak output voltage low class a1 pads v ola1 cc ?? 0.4 v i ol 2 ma; pin out driver= medium ?? 0.4 v i ol 500 a; pin out driver= weak 1) hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cant be guaranteed that it suppresses switching due to external system noise. table 7 standard_pads class_a1+ parameter symbol values unit note / test condition min. typ. max. input leakage current class a1+ i oza1+ cc -1000 ? 1000 na table 6 standard_pads class_a1 (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 12 v 0.7 preliminary, 2010-03 on-resistance of the a1+ pad, strong soft edge r dson1+ cc ?? 85 ohm i oh <2ma; i ol <2ma; p_mos ?? 70 ohm i oh <2ma; i ol <2ma; n_mos fall time, pad type a1+ t fa1+ cc ?? 150 ns c l = 20 pf; pin out driver= weak ?? 28 ns c l =50pf; edge= slow ; pin out driver= strong ?? 16 ns c l =50pf; edge= soft ; pin out driver= strong ?? 50 ns c l = 50 pf; pin out driver= medium ?? 140 ns c l = 150 pf; pin out driver= medium ?? 550 ns c l = 150 pf; pin out driver= weak ?? 18000 ns c l = 20000 pf; pin out driver= medium ?? 65000 ns c l = 20000 pf; pin out driver= weak table 7 standard_pads class_a1+ (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 13 v 0.7 preliminary, 2010-03 rise time, pad type a1+ t ra1+ cc ?? 150 ns c l = 20 pf; pin out driver= weak ?? 28 ns c l =50pf; edge= slow ; pin out driver= strong ?? 16 ns c l =50pf; edge= soft ; pin out driver= strong ?? 50 ns c l = 50 pf; pin out driver= medium ?? 140 ns c l = 150 pf; pin out driver= medium ?? 550 ns c l = 150 pf; pin out driver= weak ?? 18000 ns c l = 20000 pf; pin out driver= medium ?? 65000 ns c l = 20000 pf; pin out driver= weak input high voltage, class a1+ pads v iha1+ sr 0.6 x v ddp ? min(v ddp + 0.3,3.6 ) v input low voltage class a1+ pads v ila1+ sr -0.3 ? 0.36 x v ddp v table 7 standard_pads class_a1+ (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 14 v 0.7 preliminary, 2010-03 output voltage high class a1+ pads v oha1+ cc v ddp - 0.4 ?? v i oh -1.4 ma; pin out driver= medium v ddp - 0.4 ?? v i oh -1.4 ma; pin out driver= strong 2.4 ?? v i oh -2 ma; pin out driver= medium 2.4 ?? v i oh -2 ma; pin out driver= strong v ddp - 0.4 ?? v i oh -400 a; pin out driver= weak 2.4 ?? v i oh -500 a; pin out driver= weak output voltage low class a1+ pads v ola1+ cc ?? 0.4 v i ol 2 ma; pin out driver= medium ?? 0.4 v i ol 2 ma; pin out driver= strong ?? 0.4 v i ol 500 a; pin out driver= weak table 7 standard_pads class_a1+ (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 15 v 0.7 preliminary, 2010-03 table 8 standard_pads class_a2 parameter symbol values unit note / test condition min. typ. max. input leakage current class a2 i oza2 cc -6000 ? 6000 na v i < v ddp / 2 - 1v; v i > v ddp / 2 + 1 v; v i 0v; v i v ddp v -3000 ? 3000 na v i > v ddp / 2 - 1v; v i < v ddp / 2 + 1 v ratio vil/vih, a2 pads v ila2 / v iha2 cc 0.6 ?? on-resistance of the a2 pad, strong sharp edge r dson2 cc ?? 25 ohm i oh <2ma; i ol <2ma; p_mos ?? 20 ohm i oh <2ma; i ol <2ma; n_mos
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 16 v 0.7 preliminary, 2010-03 fall time, pad type a2 t fa2 cc ?? 150 ns c l = 20 pf; pin out driver= weak ?? 7ns c l =50pf; edge= medium ; pin out driver= strong ?? 10 ns c l =50pf; edge= medium- minus ; pin out driver= strong ?? 3.7 ns c l =50pf; edge= sharp ; pin out driver= strong ?? 5ns c l =50pf; edge= sharp- minus ; pin out driver= strong ?? 16 ns c l =50pf; edge= soft ; pin out driver= strong ?? 50 ns c l = 50 pf; pin out driver= medium ?? 7.5 ns c l = 100 pf; edge= sharp ; pin out driver= strong ?? 140 ns c l = 150 pf; pin out driver= medium table 8 standard_pads class_a2 (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 17 v 0.7 preliminary, 2010-03 ?? 550 ns c l = 150 pf; pin out driver= weak ?? 18000 ns c l = 20000 pf; pin out driver= medium ?? 65000 ns c l = 20000 pf; pin out driver= weak table 8 standard_pads class_a2 (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 18 v 0.7 preliminary, 2010-03 rise time, pad type a2 t ra2 cc ?? 150 ns c l = 20 pf; pin out driver= weak ?? 7.0 ns c l =50pf; edge= medium ; pin out driver= strong ?? 10 ns c l =50pf; edge= medium- minus ; pin out driver= strong ?? 3.7 ns c l =50pf; edge= sharp ; pin out driver= strong ?? 5ns c l =50pf; edge= sharp- minus ; pin out driver= strong ?? 16 ns c l =50pf; edge= soft ; pin out driver= strong ?? 50 ns c l = 50 pf; pin out driver= medium ?? 7.5 ns c l = 100 pf; edge= sharp ; pin out driver= strong ?? 140 ns c l = 150 pf; pin out driver= medium table 8 standard_pads class_a2 (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 19 v 0.7 preliminary, 2010-03 ?? 550 ns c l = 150 pf; pin out driver= weak ?? 18000 ns c l = 20000 pf; pin out driver= medium ?? 65000 ns c l = 20000 pf; pin out driver= weak input high voltage, class a2 pads v iha2 sr 0.6 x v ddp ? min(v ddp + 0.3, 3.6) v input low voltage class a2 pads v ila2 sr -0.3 ? 0.36 x v ddp v table 8 standard_pads class_a2 (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 20 v 0.7 preliminary, 2010-03 output voltage high class a2 pads v oha2 cc v ddp - 0.4 ?? v i oh -1.4 ma; pin out driver= medium v ddp - 0.4 ?? v i oh -1.4 ma; pin out driver= strong 2.4 ?? v i oh -2 ma; pin out driver= medium 2.4 ?? v i oh -2 ma; pin out driver= strong v ddp - 0.4 ?? v i oh -400 a; pin out driver= weak 2.4 ?? v i oh -500 a; pin out driver= weak output voltage low class a2 pads v ola2 cc ?? 0.4 v i ol 2 ma; pin out driver= medium ?? 0.4 v i ol 2 ma; pin out driver= strong ?? 0.4 v i ol 500 a; pin out driver= weak table 8 standard_pads class_a2 (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 21 v 0.7 preliminary, 2010-03 table 9 standard_pads class_f parameter symbol values unit note / test condition min. typ. max. input hysteresis f 1) 1) hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cant be guaranteed that it suppresses switching due to external system noise. hysf cc 0.05 x v ddp ?? v input leakage current class f i ozf cc -6000 ? 6000 na v i < v ddp / 2 - 1v; v i > v ddp / 2 + 1 v; v i 0v; v i v ddp v -3000 ? 3000 na v i > v ddp / 2 - 1v; v i < v ddp / 2 + 1 v fall time, pad type f, cmos mode t ff2 cc ?? 60 ns lvds cmos= cmos rise time, pad type f, cmos mode t rf1 cc ?? 60 ns lvds cmos= cmos input high voltage, pad class f, cmos mode v ihf sr 0.6 x v ddp ? min(v ddp + 0.3, 3.6) v input low voltage, class f pads, cmos mode v ilf sr -0.3 ? 0.36 x v ddp v output high voltage, class f pads, cmos mode v ohf cc v ddp- 0.4 ?? v i oh -1.4 ma 2.4 ?? v i oh -2 ma output low voltage, class f pads, cmos mode v olf cc ?? 0.4 v i ol 2ma
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 22 v 0.7 preliminary, 2010-03 table 10 standard_pads class_i parameter symbol values unit note / test condition min. typ. max. input hysteresis class i 1) 1) hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cant be guaranteed that it suppresses switching due to external system noise. hysi cc 0.1 x v ddp ?? v input leakage current i ozi cc -1000 ? 1000 na ratio between low and high input threshold v ili / v ihi cc 0.6 ?? input high voltage, class i pins v ihi sr 0.6 x v ddp ? min(v ddp + 0.3, 3.6) v input low volt age, class i pads v ili sr -0.3 ? 0.36 x v ddp v table 11 lvds_pads parameters parameter symbol values unit note / test condition min. typ. max. output impedance, pad class f, lvds mode r o cc 40 ? 140 ohm fall time, pad type f, lvds mode t ff1 cc ?? 2 ns lvds cmos= lvds rise time, pad type f, lvds mode t rf1 cc ?? 2 ns lvds cmos= lvds pad set-up time t set_lvd s cc ?? 13 s output differential voltage v od cc 150 ? 400 mv output voltage high, pad class f, lvds mode v oh cc ?? 1525 mv output volta ge low, pad class f, lvds mode v ol cc 875 ?? mv output offset voltage v os cc 1075 ? 1325 mv
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 23 v 0.7 preliminary, 2010-03 1.2.2 analog to digital converters (adcx) table 12 adc parameters parameter symbol values unit note / test condition min. typ. max. switched capacitance at the analog voltage inputs 1) c ainsw cc ? 720pf total capacitance of an analog input c aintot cc ? 25 30 pf switched capacitance at the positive reference voltage input 2)3) c arefsw cc ? 15 30 pf total capacitance of the voltage reference inputs 2) c arefto t cc ? 20 40 pf differential non-linearity error 4)5)6) ea dnl cc -3 ? 3 lsb adc resolution= 12- bit ; v ddm =3.3v 7) 8) -3 ? 3 lsb adc resolution= 12- bit ; v ddm =5.0v 7) 8) gain error 4)5)6) ea gain cc -3.5 ? 3.5 lsb adc resolution= 12- bit ; v ddm =3.3v 7) 8) -3.5 ? 3.5 lsb adc resolution= 12- bit ; v ddm =5.0v 7) 8)
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 24 v 0.7 preliminary, 2010-03 integral non-linearity 4)5)6) ea inl cc -3 ? 3 lsb adc resolution= 12- bit ; v ddm =3.3v 7) 8) -3 ? 3 lsb adc resolution= 12- bit ; v ddm =5.0v 7) 8) offset error 4)5)6) ea off cc -4 ? 4 lsb adc resolution= 12- bit ; v ddm =3.3v 7) 8) -4 ? 4 lsb adc resolution= 12- bit ; v ddm =5.0v 7) 8) internal adc clock f adci cc 1 ? 20 mhz reference =va ref ; v ddm =5.0v current through resistance for the adc test (pull-down for ain7) i ain7t cc ? 15 tbd ma input current at varef input per module 2) i aref cc ?? 75 a v arefx v ddm v ; v arefx 0v 9)10) table 12 adc parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 25 v 0.7 preliminary, 2010-03 input leakage at analog inputs 11) i oz1 cc -100 ? 500 na v i v ddm v; v i 0.97 x v ddm v; overlayed= no -100 ? 600 na v i 0.97 x v ddm v; v i v ddm v; overlayed= yes -500 ? 100 na v i 0.03 x v ddm v; v i 0v; overlayed= no -600 ? 100 na v i 0.03 x v ddm v; v i 0v; overlayed= yes -100 ? 200 na v i > 0.03 x v ddm v; v i < 0.97 x v ddm v; overlayed= no -100 ? 300 na v i < 0.97 x v ddm v; v i > 0.03 x v ddm v; overlayed= yes input leakage current at varef i oz2 cc -1 ? 1 a v arefx 0v; v arefx v ddm v input leakage current at vagnd i oz3 cc -1 ? 1 a v agndx 0v; v agndx v ddm v on resistance of the transmition gates in the analog voltage path r ain cc ? 700 1500 ohm v ddm =5v on resistance for the adc test (pull down for ain7) r ain7t cc 180 550 900 ohm table 12 adc parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 26 v 0.7 preliminary, 2010-03 resistance of the reference voltage input path r aref cc ? 500 1000 ohm total unadjusted error 5)6)12) tue cc -4 ? 4 lsb adc resolution= 12- bit ; v ddm =3.3v -4 ? 4 lsb adc resolution= 12- bit ; v ddm =5.0v analog reference ground 2) v agndx sr v ssm - 0.05 ? v arefx - 1 v analog input voltage v ain sr v agndx ? v ddm v analog reference voltage 2) v arefx sr v agndx + 1 ? v ddm + 0.05 13) 14) v analog reference voltage range 5)6)2) v arefx - v agndx sr v ddm /2 ? v ddm + 0.05 v 1) the sampling capacity of the conversion c-network is pre-charged to v aref /2 before the sampling moment. because of the parasitic elements the voltage measured at ainx can deviate from v aref /2. 2) applies to ainx, when used as auxiliary reference input. 3) this represents an equivalent switched capacitance. this capacitance is not switched to the reference voltage at once. instead smaller capacitances are successively switched to the reference voltage. 4) the sum of dnl/inl/gain/off errors does not exceed the related tue total unadjusted error. 5) if the analog reference voltage range is below v ddm but still in the defined range of v ddm / 2 and v ddm is used, then the adc converter errors increase. if the reference voltage is reduced by the factor k (k<1), tue,dnl,inl,gain, and offset errors increase also by the factor 1/k. 6) if a reduced analog reference voltage between 1v and v ddm / 2 is used, then there are additonal decrease in the adc speed and accuracy. 7) for 10-bit conversions the error value must be multiplied with a factor 0.25. 8) for 8-bit conversions the error value must be multiplied with a factor 0.0625. 9) i aref_max is valid for the minimum specified conversion time. the current flowing during an adc conversion with a duration of up to t c = 25 s can be calculated with the formula i aref_max = q conv / t c . every conversion needs a total charge of q conv = 150 pc from v aref . 10) all adc conversions with a duration longer than t c = 25 s consume an i aref_max = 6 a. table 12 adc parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 27 v 0.7 preliminary, 2010-03 the power-up calibration of the adc requires a ma ximum number of 4352 f adci cycles. figure 1 adcx input circuits 11) the leakage current definition is a continous function,as shown in figure adcx analoge input leakage. the numerical values defined determine the characteristic points of the given countinuous linear approximation - they do not define step function. 12) measured without noise. 13) a running conversion may become inexact in case of violating the normal conditions (voltage overshoot). 14) if the reference voltage v aref increase or the v ddm decrease, so that v aref = ( v ddm + 0.05v to v ddm + 0.07v), then the accuracy of the adc decrease by 4lsb12. table 13 conversion time (operating conditions apply) parameter symbol values unit note conversion time with post-calibration t c cc 2 t adc +(4+stc+n) t adci s n = 8, 10, 12 for n - bit conversion t adc =1/ f fpi t adci =1/ f adci conversion time without post-calibration 2 t adc +(2+stc+n) t adci reference voltage input circuitry analog input circuitry analog_inprefdiag r ext = v ain c ext r ain, on c aintot - c ainsw c ainsw anx v aref r aref, on c areftot - c arefsw c arefsw v agndx v arefx r ain7t v agndx
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 28 v 0.7 preliminary, 2010-03 figure 2 adcx analog inputs leakage v in [v ddm %] 200na 500na 3% 100% 97% ioz1 100na -500na -100na v in [v ddm %] 300na 600na 3% 100% 97% ioz1 100na -600na -100na single adc input overlayed adc/fadc input
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 29 v 0.7 preliminary, 2010-03 1.2.3 fast analog to digital converter (fadc) table 14 fadc parameters parameter symbol values unit note / test condition min. typ. max. input current at each vfaref i faref cc ?? 120 a input leakage current at vfaref 1) i foz2 cc -500 ? 500 na v faref v ddmf v; v faref 0v input leakage current at vfagnd i foz3 cc -8 ? 8 a dnl error ef dnl cc -1 ? 1lsb v in mode= differential -1 ? 1lsb v in mode= single ended gradient error ef grad cc -5 ? 5% v in mode= differential ; calibration= no ; gain 4 -5 ? 5% v in mode= single ended ; calibration= no ; gain 4 -6 ? 6% v in mode= differential ; calibration= no ; gain= 8 -6 ? 6% v in mode= single ended ; calibration= no ; gain= 8 inl error ef inl cc -4 ? 4lsb v in mode= differential -4 ? 4lsb v in mode= single ended
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 30 v 0.7 preliminary, 2010-03 offset error ef off cc -90 ? 90 mv v in mode= differential ; calibration= no 2) -90 ? 90 mv v in mode= single ended ; calibration= no 2) -20 ? 20 mv v in mode= differential ; calibration= ye s 3)4)2) -20 ? 20 mv v in mode= single ended ; calibration= ye s 3)4)2) reference error of internal vfaref/2 ef ref cc -60 ? 60 mv channel amplifier cutoff frequency f coff cc 2 ?? mhz input resistance of the analog volta ge path (rn, rp) r fain cc 100 ? 200 koh m settling time of a channel amplifier after changing enn or enp t set cc ?? 5 s analog input voltage range v ainf sr v fagnd ? v ddmf v analog reference ground v fagnd sr v ssaf - 0.05 ? v ssaf + 0.05 v analog reference voltage v faref sr 3.0 ? 3.63 5) 6) v 1) this value applies in power-down mode. 2) applies when the gain of the channel equals one. for the other gain settings, the offset error increases; it must be mulitplied with the applied gain. table 14 fadc parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 31 v 0.7 preliminary, 2010-03 the calibration procedure should run afte r each power-up, wh en all power supply voltages and the referenc e voltage have stabilized. figure 3 fadc input circuits 3) calibration should be preformed at each power-up. in case of a continous operation, it should be performed minimium once per week. 4) the offser error voltage drifts over the whole temperature range maximum +-3lsb. 5) voltage overshoot to 4v is permissible, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 6) a running conversion may become inexact in case of violating the nomal operating conditions (voltage overshoots). fadc_inprefdiag = + - + - r n fainxn fainxp v fag nd fadc analog input stage r p v faref /2 v faref fadc reference voltage input circuitry v fag nd v faref i faref
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 32 v 0.7 preliminary, 2010-03 1.2.4 oscillator pins note: it is strongly recommended to meas ure the oscillation allowance (negative resistance) in the final target system (lay out) to determine t he optimal parameters for the oscillator operation. please refer to the limits specified by the crystal or ceramic resonator supplier. table 15 osc_xtal parameters parameter symbol values unit note / test condition min. typ. max. input current at xtal1 i ix1 cc -25 ? 25 a v in < v ddosc3 ; v in >0 v input frequency f osc sr 4 ? 40 mhz direct input mode selected 8 ? 25 mhz external crystal mode selected oscillator start-up time 1) 1) t oscs is defined from the moment when v ddosc3 = 3.13v until the oscillations reach an amplitude at xtal1 of 0.3 * v ddosc3 . the external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystral suppliers. t oscs cc ?? 10 ms input high voltage at xtal1 2) 2) if the xtal1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.4 * v ddosc3 is necessary. v ihx sr 0.7 x v ddos c3 ? v ddos c3 + 0.2 v input low voltage at xtal1 v ilx sr -0.2 ? 0.3 x v ddos c3 v
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 33 v 0.7 preliminary, 2010-03 1.2.5 temperature sensor the following formula calc ulates the temperature me asured by the dts in [ o c] from the result bit field of the dtsstat register. (1) table 16 dts parameters parameter symbol values unit note / test condition min. typ. max. measurement time t m cc ?? 100 s temperature sensor range t sr sr -40 ? 150 c sensor accuracy (calibrated) t tsa cc -6 ? 6c t j 120 c -3 ? 3c t j >120c start-up time after resets inactive t tsst sr ?? 20 s tbd
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 34 v 0.7 preliminary, 2010-03 1.2.6 power supply current the total power supply current defined below consists of leakage and switching component. application relevant values are typically lowe r than those given in the following two tables and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations). the operating conditions for the parameters in the following table are: v dd =1.365 v, v ddp =3.47 v, f lmb =180 / 133 mhz, t j =150 o c table 17 power supply parameters parameter symbol values unit note / test condition min. typ. max. core active mode supply current 1)2) i dd cc ?? 595 3) ma power pattern= max ; product = sak- tc1782-256f 133hl ?? 670 3) ma power pattern= max ; product = sak- tc1782-320f 180hl ?? 480 4) ma power pattern= realisti c; product = sak- tc1782-256f 133hl ?? 542 4) ma power pattern= realisti c; product = sak- tc1782-320f 180hl i dd current at porst low i dd_pors t cc ?? 180 ma
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 35 v 0.7 preliminary, 2010-03 flash memory current during continuously erasing-verifying the flash memory 5) i ddfl3e cc ?? 61 6) ma flash memory current during continuously reading the flash memory 5) i ddfl3r cc ?? 56 ma v ddp =3.47v adc 5v power supply current i ddm cc ?? 2ma fadc analog supply current, 3.3v i ddmf cc ?? 15 ma oscillator core supply current i ddosc cc ?? 4ma oscillator power supply current, 3.3v i ddosc3 cc ?? 15 ma pad current relevant for thermal calculation, no pad activity, lvds off i ddp cc ?? 15 ma i ddp current during flash memory programming and erasing 5)7) i ddp_fp cc ?? 55 ma i dd current at porst low i ddp_por st cc ?? 2ma current consumption of lvds pad pairs i lvds cc ?? 24 ma table 17 power supply parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersdc parameters target data sheet/acdc target specif ication 36 v 0.7 preliminary, 2010-03 maximum power dissipation pd cc ?? 1230 mw power pattern= max ; product = sak- tc1782-256f 133hl ?? 1333 mw power pattern= max ; product = sak- tc1782-320f 180hl ?? 1042 mw power pattern= realisti c; product = sak- tc1782-256f 133hl ?? 1124 mw power pattern= realisti c; product = sak- tc1782-320f 180hl thermal resistance junction to ambient r thja cc ?? tbd k/w package= pg- lqfp-176-x analog core supply current i ddaf cc ?? 17 ma 1) infineon power loop: cpu and pcp running, all peripherals active. the power consumption of each customer application will most probably be lower than this value, but must be evaluated seperately. 2) this current includes the e-ray module power consumption, including the pcp operation component. 3) the i dd decreases typically by 83ma if the f cpu decreases by 50mhz, at constant t j 4) the i dd decreases typically by 65ma if the f cpu decreases by 50mhz, at constant t j 5) relevant for the power supply dimensioning, not for thermal considerations. 6) in case of erase of program flash pf0, internal fl ash array loading effects may generate transient current spikes of up to 100 ma for maximum 5 ms. 7) the currenty caused by the gpio activity depend on the particular application and should be added seperately. table 17 power supply parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 37 v 0.7 preliminary, 2010-03 1.3 ac parameters all ac parameters are defi ned with the temperature compensation disabled. that means, keeping the pads consta ntly at maximum strength. 1.3.1 testing waveforms figure 4 rise/fall time parameters figure 5 testing waveform, output delay figure 6 testing waveform, output high impedance 10% 90 % 10% 90% v ss v ddp t r rise_fall t f mct04881_a.vsd v dde / 2 test points v dde / 2 v ss v ddp mct04880_new v load + 0.1 v v oh - 0.1 v timing reference points v load - 0.1 v v ol - 0.1 v
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 38 v 0.7 preliminary, 2010-03 1.3.2 power sequencing figure 7 5 v / 3.3 v / 1.3 v power-up/down sequence the following list of rules applie s to the power-up/down sequence: ? all ground pins v ss must be externally c onnected to one single star point in the system. regarding the dc current component, all ground pins are internally directly connected. ? at any moment in time to avoid increased latch-up risk, each power supply must be higher then any lower_power_supply - 0.5 v, or: v dd5 > v dd3.3 - 0.5 v; v dd5 > v dd1.3 - 0.5 v; v dd3.3 > v dd1.3 - 0.5 v, see figure 7 . ? the latch-up risk is minimized if the i/o currents are limited to: ? 20 ma for one pin group ? and 100 ma for the co mpleted device i/os ? and additionally before po wer-up / after power-down: 1 ma for one pin in inactive mode (0 v on all power supplies) ? during power-up and power-dow n, the voltage difference between the power supply pins of the same voltage (3.3 v, 1.3 v, and 5 v) with di fferent names (for example v ddp , v ddfl3 ...), that are internal ly connected via diodes, must be lower than 100 mv. on the other hand, all power supply pins with the same name (for example all v ddp ), power-up 10.vsd 1.3v 3.3v 5v t v t -12% -12% porst 0.5v 0.5v 0.5v v ddp v aref power down power fail 3.47v 3.0v 1.235v 1.365v 4.75v 5.25v
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 39 v 0.7 preliminary, 2010-03 are internally directly con nected. it is recommended that the power pins of the same voltage are driven by a single power supply. 1. the porst signal may be deac tivated after all v dd5 , v dd3.3 , v dd1.3 , and v aref power- supplies and the oscillator have reache d stable operation, within the normal operating conditions. 2. at normal power down the porst signal should be acti vated within the normal operating range, and th en the power supplies may be s witched off. care must be taken that all flash write or delet e sequences have been completed. 3. at power fail the porst signal must be activated at latest when any 3.3 v or 1.3 v power supply voltage falls 12% below the nominal level. if, under these conditions, the porst is activated during a flash write, only the memory row that was the target of the write at the moment of the power loss wil l contain unreliable content. in order to ensure clean power-d own behavior, the porst signal should be activated as close as possible to the no rmal operating voltage range. 4. in case of a power-loss at any power-s upply, all power suppl ies must be powered- down, conforming at th e same time to the rules number 2 and 4. 5. although not necessar y, it is additionally recomm ended that all power supplies are powered-up/down together in a controlled way, as tight to each other as possible. 6. additionally, regarding the adc reference voltage v aref : ? v aref must power-up at the sa me time or later then v ddm , and ? v aref must power-down either earlier or at latest to satisfy the condition v aref < v ddm + 0.5 v. this is required in or der to prevent discharge of v aref filter capacitance through the esd diodes through the v ddm power supply. in case of discharging the reference capacitance th rough the esd diodes, the current must be lower than 5 ma.
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 40 v 0.7 preliminary, 2010-03 1.3.3 power, pad and reset timing table 18 reset ti mings parameters parameter symbol values unit note / test condition min. typ. max. application reset boot time 1)2) 1) the duration of the boot time is defined between the rising edge of the internal application reset and the clock cycle when the first user instruction has ent ered the cpu pipeline and its processing starts. 2) the given time includes the time of the internal reset extension for a configured value of scu_rstcntcon.relsa = 0x05be. t b cc 150 ? 810 s product = sak- tc1782-256f 133hl 150 ? 665 s product = sak- tc1782-320f 180hl power on reset boot time 3)4) 3) the duration of the boot time is defined between the rising edge of the porst and the clock cycle when the first user instruction has entered the cpu pipeline and its processing starts. t bp cc ?? 2.5 ms hwcfg pins hold time from esr0 rising edge t hdh sr 16 / f fpi ?? ns hwcfg pins setup time to esr0 rising edge t hds cc 0 ?? ns ports inactive after esr0 reset active t pi cc ?? 8 / f fpi ns ports inactive after porst reset active 5) t pip cc ?? 150 ns minimum porst active time after power supplies are stable at operating levels t poa cc 10 ?? ms hold time from porst rising edge t poh sr 100 ?? ns porst rise time t por sr ?? 50 ms setup time to porst rising edge t pos sr 0 ?? ns
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 41 v 0.7 preliminary, 2010-03 figure 8 power, pad and reset timing 4) the given time includes the internal reset extension ti me for the system and application reset which is visible through esr0. 5) this parameter includes the delay of the analog spike filter in the porst pad. reset_beh2 as programmed vddp pads pad- state undefined vdd v ddppa v d d ppa t hd t poa t poa trst testmode esr0 porst t poh hwcfg t hdh t pip t pi tri -state or pull device active t hd t poh t hdh t pip t pi t pip t pi t pi t hdh t pi v ddp -12% v dd -12%
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 42 v 0.7 preliminary, 2010-03 1.3.4 phase locked loop (pll) phase locked loop operation when pll operation is enabled and configured, the pll clock f vco (and with it the lmb- bus clock f lmb ) is constantly adjusted to the sele cted frequency. the pll is constantly adjusting its output freq uency to correspond to the input frequency (from crystal or clock source), resulting in an accumulated jitter th at is limited. this me ans that the relative deviation for periods of more than one clock cycle is lower than for a single clock cycle. this is especially important for bus cycles using wait states and for the operation of timers, serial interfaces, etc. for all slower operations and longer per iods (e.g. pulse train generation or measurement, lo wer baudrates, etc.) the deviation caused by the pll jitter is negligible. two formulas are defined fo r the (absolute) approximate maximum value of jitter d m in [ns] dependent on the k2 - facto r, the lmb clock frequency f lmb in [mhz], and the number m of consecutive f lmb clock periods. (2) (3) with rising number m of clock cycles the maximum jitter increases linearly up to a value of m that is defined by th e k2-factor of the pll. beyond this value of m the maximum table 19 pll_sysclk parameters parameter symbol values unit note / test condition min. typ. max. accumulated jitter d p cc -7 ? 7ns pll base frequency f pllbase cc 50 200 320 mhz vco input frequency f ref cc 8 ? 16 mhz vco frequency range f vco cc 400 ? 720 mhz pll lock-in time t l cc ?? 200 s for k2 100 () and m f lmb mhz [] () 2 ? () d mns [] 740 k2 f lmb mhz [] -------------------------------------------- -5 + ?? ?? 1001 , k2 ? () m1 ? () 05 , f lmb mhz [] 1 ? -------------------------------------------- -------------------- 0 0 1 , k2 + ?? ?? = else d mns [] 740 k2 f lmb mhz [] -------------------------------------------- -5 + =
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 43 v 0.7 preliminary, 2010-03 accumulated jitter remains at a constant value. further, a lower lmb-bus clock frequency f lmb results in a hi gher absolute maxi mum jitter value. note: the specified pll jitter values are va lid if the capacitive load per pin does not exceed c l = 20 pf with the maximum driver and sharp edge. note: the maximum peak-to-peak noise on the pad supply volta ge, measured between v ddosc3 and v ssosc , is limited to a peak-to-peak voltage of v pp = 100 mv for noise frequencies below 300 khz and v pp = 40 mv for noise frequencies above 300 khz. the maximum peak-to peak noise on the pad supply voltage , measured between v ddosc and v ssosc , is limited to a pe ak-to-peak voltage of v pp = 100 mv for noise frequencies below 300 khz and v pp = 40 mv for noise frequencies above 300 khz. these conditions can be achi eved by appropriate blo cking of the supply voltage as near as possible to the supply pins and using pcb suppl y and ground planes. oscillator watchdog (osc_wdt) the expected input fr equency is selected via the bi t field scu_osccon.oscval. the osc_wdt checks for too low frequenc ies and for too high frequencies. the frequency that is monitored is f oscref which is derived for f osc . (4) the divider value scu_osccon.oscval has to be selected in a way that f oscref is 2.5 mhz. note: f oscref has to be within the range of 2 mhz to 3 mhz and should be as close as possible to 2.5 mhz. the monitored frequency is too low if it is below 1.25 mhz and too high if it is above 7.5 mhz. this leads to the following two conditions: ? too low: f osc <1.25mhz (scu_osccon.oscval+1) ? too high: f osc >7.5mhz (scu_osccon.oscval+1) note: the accuracy is 30 % for these boundaries. f oscref f osc oscval 1 + ---------------------------------- - =
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 44 v 0.7 preliminary, 2010-03 1.3.5 eray phase locked loop (eray_pll) note: the specified pll jitter values are va lid if the capacitive load per pin does not exceed c l = 20 pf with the maximum driver and sharp edge. note: the maximum peak-to-peak noise on the pad supply volta ge, measured between v ddosc3 and v ssosc , is limited to a peak-to-peak voltage of v pp = 100 mv for noise frequencies below 300 khz and v pp = 40 mv for noise frequencies above 300 khz. these conditions can be achi eved by appropriate blo cking of the supply voltage as near as possible to the supply pins and using pcb suppl y and ground planes. table 20 pll_eray parameters parameter symbol values unit note / test condition min. typ. max. accumulated jitter at sysclk pin d pp cc -0.8 ? 0.8 ns accumulated_jitter d p cc -0.5 ? 0.5 ns pll base frequency of the eray pll f pllbase_ eray cc 50 200 360 mhz vco input frequency of the eray pll f ref cc 20 ? 40 mhz vco frequency range of the eray pll f vco_era y cc 450 ? 500 mhz pll lock-in time t l cc ?? 200 s
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 45 v 0.7 preliminary, 2010-03 1.3.6 jtag interface timing the following parameters are applicable for communicati on through the jtag debug interface. the jtag module is fully compli ant with ieee1149.1-2000. note: these parameters are not subject to pr oduction test but veri fied by design and/or characterization. table 21 jtag interface timing parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. tck clock period t 1 sr25??ns? tck high time t 2 sr10??ns? tck low time t 3 sr10??ns? tck clock rise time t 4 sr??4ns? tck clock fall time t 5 sr??4ns? tdi/tms setup to tck rising edge t 6 sr6??ns? tdi/tms hold after tck rising edge t 7 sr6??ns? tdo valid after tck falling edge 1) (propagation delay) 1) the falling edge on tck is used to generate the tdo timing. t 8 cc??13nsc l =50pf t 8 cc3??nsc l =20pf tdo hold after tck falling edge 1) t 18 cc2??ns tdo high imped. to valid from tck falling edge 1)2) 2) the setup time for tdo is given implicitly by the tck cycle time. t 9 cc??14nsc l =50pf tdo valid to high imped. from tck falling edge 1) t 10 cc ? ? 13.5 ns c l =50pf
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 46 v 0.7 preliminary, 2010-03 figure 9 test clock timing (tck) figure 10 jtag timing mc_jtag_tck 0.9 v ddp 0.5 v ddp t 1 t 2 t 3 0.1 v ddp t 5 t 4 t 6 t 7 t 6 t 7 t 9 t 8 t 10 tck tms tdi tdo mc_jtag t 18
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 47 v 0.7 preliminary, 2010-03 1.3.7 dap interface timing the following para meters are applicable for comm unication throu gh the dap debug interface. note: these parameters are not subject to pr oduction test but veri fied by design and/or characterization. figure 11 test clock timing (dap0) table 22 dap parameters parameter symbol values unit note / test condition min. typ. max. dap0 clock period 1) 1) see the dap chapter for clock rate restrictions in the active:idle protocol state. t tck sr 12.5 ?? ns dap0 high time t 12 sr 4 ?? ns dap0 low time 1) t 13 sr 4 ?? ns dap0 clock rise time t 14 sr ?? 2ns dap0 clock fall time t 15 sr ?? 2ns dap1 setup to dap0 rising edge t 16 sr 6.0 ?? ns dap1 hold after dap0 rising edge t 17 sr 6.0 ?? ns dap1 valid per dap0 clock period 2) 2) the host has to find a suitable sampling point by analyzing the sync telegram response. t 19 sr 8 ?? ns c l =20pf; f =80mhz 10 ?? ns c l =50pf; f =40mhz mc_dap0 0.9 v ddp 0.5 v ddp t 11 t 12 t 13 0.1 v ddp t 15 t 14
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 48 v 0.7 preliminary, 2010-03 figure 12 dap timing host to device figure 13 dap timing device to host t 16 t 17 dap0 dap1 mc_dap1_rx dap1 mc_ dap1_tx t 11 t 19
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 49 v 0.7 preliminary, 2010-03 1.3.8 peripheral timings note: peripheral timing parameters are not su bject to production test. they are verified by design/characterization. 1.3.8.1 micro link interface (mli) timing figure 14 mli interface timing note: the generation of rreadyx is in t he input clock domain of the receiver. the reception of treadyx is asynchronous to tclkx. t 27 t 25 t 26 t 16 t 17 t 15 t 15 mli_tmg_2.vsd tdatax tvalidx tclkx rdatax rvalidx rclkx treadyx rreadyx t 10 t 13 t 11 t 12 t 14 t 20 t 27 mli transmitter timing mli receiver timing t 23 t 21 t 22 t 24
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 50 v 0.7 preliminary, 2010-03 table 24 is valid under the followi ng conditions: edge=medium table 23 mli receiver parameter symbol values unit note / test condition min. typ. max. rclk clock period t 20 sr 1 / f fpi ?? ns rclk high time 1)2) 1) the following formula is valid: t21 + t22 = t20. 2) min and max values for this parameter can be derived from the typ. value by considering the other receiver timing parameters. t 21 sr ? 0.5 x t 20 ? ns rclk low time 1)2) t 22 sr ? 0.5 x t 20 ? ns rclk rise time 3) 3) the rclk max. input rise/fall times are best case par ameters for fsys = 90 mhz. for reduction of emi, slower input signal rise/fall times can be used for longer rclk clock periods. t 23 sr ?? 4ns rclk fall time 3) t 24 sr ?? 4ns rdata/rvalid setup time before rclk falling edge t 25 sr 4.2 ?? ns rdata/rvalid hold time after rclk falling edge t 26 cc 2.2 ?? ns rready output delay time t 27 cc 0 ? 16 ns table 24 mli transmitter parameter symbol values unit note / test condition min. typ. max. tclk clock period t 10 cc 2 x 1 / f fpi ?? ns tclk high time 1)2) t 11 cc 0.45 x t 10 0.5 x t 10 0.55 x t 10 ns tclk low time 1)2) t 12 cc 0.45 x t 10 0.5 x t 10 0.55 x t 10 ns tclk rise time t 13 cc ?? 16 3) ns
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 51 v 0.7 preliminary, 2010-03 1.3.8.2 micro second channel (msc) interface timing tclk fall time t 14 cc ?? 16 3) ns tdata/tvalid output delay time t 15 cc -3 ? 4.4 ns tready setup time before tclk rising edge t 16 sr 18 ?? ns tready hold time after tclk rising edge t 17 sr -4 ?? ns 1) the following formula is valid: t11 + t12 = t10. 2) the min./max. tclk low/high times t11/t12 include the pl l jitter of fsys. fractional divider settings must be regarded additionally to t11 / t12. 3) for high-speed mli interface, strong driver sharp or medium edge selection (class a2 pad) is recommended for tclk. table 25 msc parameters parameter symbol values unit note / test condition min. typ. max. fclp clock period 1)2) 1) fclp signal rise/fall times are only defined by the pad rise/fall times. 2) fclp signal high and low can be minimum 1 tmsc t 40 cc 2 x t msc 3) 3) tmsc = tsys = 1 / fsys. ?? ns sop/enx outputs delay from fclp rising edge t 45 cc -10 ? 10 ns sdi bit time t 46 cc 8 x t msc ?? ns sdi rise time t 48 sr ?? 100 ns sdi fall time t 49 sr ?? 100 ns table 24 mli transmitter (cont?d) parameter symbol values unit note / test condition min. typ. max.
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 52 v 0.7 preliminary, 2010-03 figure 15 msc interface timing note: the data at sop should be sampled with the falling edge of fclp in the target device. msc_tmg_1.vsd t 45 t 45 t 40 0.1 v ddp 0.9 v ddp t 46 t 48 0.1 v ddp 0.9 v ddp t 49 t 46 sop en fclp sdi
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 53 v 0.7 preliminary, 2010-03 1.3.8.3 ssc master/slave mode timing table 26 ssc parameters parameter symbol values unit note / test condition min. typ. max. sclk clock period 1)2)3) 1) sclk signal rise/fall times are the same as the rise/fall times of the pad. 2) sclk signal high and low times can be minimum 1xtssc. 3) tsscmin = tsys = 1/fsys. t 50 cc 2 x 1 / f fpi ?? ns mtsr/slsox delay form sclk rising edge t 51 cc 0 ? 8ns mrst setup to sclk falling edge 3) t 52 sr 16.5 ?? ns mrst hold from sclk falling edge 3) t 53 sr 0 ?? ns sclk input clock period 1)3) t 54 sr 4 x 1 / f fpi ?? ns sclk input clock duty cycle t 55 _ t 54 sr 45 ? 55 % mtsr setup to sclk latching edge 3)4) 4) fractional divider switched off, ssc internal baud rate generation used. t 56 cc 1 / f fpi ?? ns mtsr hold from sclk latching edge t 57 cc 1 / f fpi + 5 ?? ns slsi setup to first sclk latching edge t 58 cc 1 / f fpi + 5 ?? ns slsi hold from last sclk latching edge t 59 cc 7 ?? ns mrst delay from sclk shift edge t 60 cc 0 ? 16.5 ns slsi to valid data on mrst t 61 cc ?? 16.5 ns
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 54 v 0.7 preliminary, 2010-03 figure 16 ssc master mode timing figure 17 ssc slave mode timing ssc_tmgmm sclk 1)2) mtsr 1) t 51 t 51 mrst 1) t 53 data valid t 52 slson 2) t 51 1) this timing is based on the following setup: con.ph = con.po = 0. 2) the transition at slson is based on the following setup: ssotc.trail = 0 and the first sclk high pulse is in the first one of a transmission. t 50 ssc_tmgsm sclk 1) t 55 mtsr 1) t 57 data valid t 56 slsi t 58 1) this timing is based on the following setup: con.ph = con.po = 0. t 54 t 55 t 59 last latching sclk edge first latching sclk edge t 57 data valid t 56 mrst 1) t 60 first shift sclk edge t 60 t 61
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 55 v 0.7 preliminary, 2010-03 1.3.8.4 eray interface timing c l = 25 pf the eray interface is only available for t he sak-tc1782-320f180hl. table 27 eray parameters parameter symbol values unit note / test condition min. typ. max. time span from last bss to fes without the influence of quartz tolerancies (d10bit_tx) 1) 1) this includes the pll_eray accumulated jitter. t 60 cc 997.25 ? 1002.2 5 ns txd data valid from fsample flip flop txd_reg txda, txdb (dtxasym) 2)3) 2) refers to delays caused by the asymmetries of the output drivers of the digital logic and the gpio pad drivers. quarz tolerance and pll_eray accumulated jitter are not included. 3) e-ray txd output drivers have an asymmetry of rising and falling edges of | t fa2 - t ra2 | 1 ns. t 61 - t 62 cc ?? 1.5 ns asymmetrical delay of rising and falling edge (txda, txdb) time span between last bss and fes without influence of quartz tolerancies (d10bit_rx) 1)4)5) 4) the min limit correspond to 30% * v ddp flexray standard input thresholds. the max limit correspond to 70% * v ddp flexray standard input thresholds. due to different input thresholds for this product, a correction of - 0.5 ns and +0.1 ns has been applied. 5) valid for output slopes of the bus driver of drxslope 5ns, 20% * v ddp to 80% * v ddp , according to the flexray electrical physical layer specification v2.1b. for a2 pads, the rise and fall times of the incoming signal have to satisfy the following inequality: -1.6ns t fa2 - t ra2 1.3ns. t 63 sr 967 ? 1046.1 ns rxd capture by fsample (rxda/rxdb sampling flip-flop) (drxasym) 6) 6) valid for output slopes of the bus driver of drxslope 5ns, 20% * v ddp to 80% * v ddp , according to the flexray electrical physical layer specification v2.1b. for a2 pads, the rise and fall times of the incoming signal have to satisfy the following inequality: -1.6ns t fa2 - t ra2 1.3ns. t 64 - t 65 cc ?? 3.0 ns asymmetrical delay of rising and falling edge (rxda, rxdb)
tc1782 electrical parametersac parameters target data sheet/acdc target specif ication 56 v 0.7 preliminary, 2010-03 figure 18 eray timing txd t 60 0.7 v dd 0.3 v dd bss (byte start sequence) last crc byte fes (frame end sequence) eray_timing rxd t 63 0.7 v dd 0.3 v dd bss (byte start sequence) last crc byte fes (frame end sequence) 0.9 v dd 0.1 v dd txd t 61 t 62 t sample 0.9 v dd 0.1 v dd rxd t 64 t 65 t sample
tc1782 electrical parametersp ackage and reliability target data sheet/acdc target specif ication 57 v 0.7 preliminary, 2010-03 1.4 package and reliability 1.4.1 package parameters table 28 thermal characteristics of the package device package r jct 1) 1) the top and bottom thermal resistances between the case and the ambient ( r tcat , r tcab ) are to be combined with the thermal resistances between the junction and the case given above ( r tjct , r tjcb ), in order to calculate the total thermal resistance between the junction and the ambient ( r tja ). the thermal resistances between the case and the ambient ( r tcat , r tcab ) depend on the external system (pcb, case) characteristics, and are under user responsibility. the junction temperature can be calculated using the following equation: t j = t a + r tja p d , where the r tja is the total thermal resistance between the junction and the ambient. this total junction ambient resistance r tja can be obtained from the upper four partial thermal resistances. thermal resistances as measured by the ?cold plate method? (mil spec-883 method 1012.1). r jcb 1) r jlead 2) 2) with connected epad. unit note tc1782 pg-lqfp-176-6 8,1 0,3 30,9 k/w
tc1782 electrical parametersp ackage and reliability target data sheet/acdc target specif ication 58 v 0.7 preliminary, 2010-03 1.4.2 package outline figure 19 package outl ines pg-lqfp-176-6 you can find all of our pack ages, sorts of packing and ot hers in our in fineon internet page ?products?: http://www.infineon.com/products . 1.4.3 flash memory parameters the data retention time of the tc1782?s flash memory depends on the num ber of times the flash memory has be en erased and programmed. exposed dipad
tc1782 electrical parametersp ackage and reliability target data sheet/acdc target specif ication 59 v 0.7 preliminary, 2010-03 table 29 flash32 parameters parameter symbol values unit note / test condition min. typ. max. data flash erase time per sector t erd cc ?? 3s program flash erase time per 256 kbyte sector t erp cc ?? 5s program time data flash per page 1) 1) in case the program verify feature detects weak bits, these bits will be programmed up to twice more. each reprogramming takes additional 5 ms. t prd cc ? 515ms program time program flash per page 2) 2) in case the program verify feature detects weak bits, these bits will be programmed once more. the reprogramming takes additional 5 ms. t prp cc ? 510ms data flash endurance n e cc 60000 3) ?? cycle s max. data retention time 5 years erase suspend delay t fl_ersusp cc ?? 15 ms wait time after margin change t fl_margin del cc 10 ?? s program flash retention time, physical sector 4)5) t ret cc 20 ?? year s max. 1000 erase/program cycles program flash retention time, logical sector 4)5) t retl cc 20 ?? year s max. 100 erase/program cycles ucb retention time 4)5) t rtu cc 20 ?? year s max. 4 erase/program cycles per ucb wake-up time t wu cc ?? 270 s dflash wait state configuration ws df cc 50 ns x f fsi ?? pflash wait state configuration ws pf cc 26 ns x f fsi ??
tc1782 electrical parametersp ackage and reliability target data sheet/acdc target specif ication 60 v 0.7 preliminary, 2010-03 the following constraints regarding flash performance apply additionally for 3.0 v 125 o c, no program / delete of pflash at all. 1.4.4 quality declarations 3) only valid when a robust eeprom emulation algorithm is used. for more details see the users manual. 4) storage and inactive time included. 5) at average weighted junction temperature t j = 100c, or the retention time at average weighted temperature of t j = 110c is minimum 10 years, or the retention time at average weighted temperature of t j = 150c is minimum 0.7 years. table 30 quality parameters parameter symbol values unit note / test condition min. typ. max. operation lifetime 1) 1) this lifetime refers only to the time when the device is powered on. t op ? ? 24000 hours ? 2) 2) for worst-case temperature profile equivalent to: 1200 hours at t j = 125...150 o c 3600 hours at t j = 110...125 o c 7200 hours at t j = 100...110 o c 11000 hours at t j = 25...110 o c 1000 hours at t j = -40...25 o c esd susceptibility according to human body model (hbm) v hbm ? ? 2000 v conforming to jesd22-a114-b esd susceptibility of the lvds pins v hbm1 ?? 500v ? esd susceptibility according to charged device model (cdm) v cdm ? ? 500 v conforming to jesd22-c101-c moisture sensitivity level msl ? ? 3 ? conforming to jedec j-std-020c for 240c
tc1782 electrical parameterspin reliability in overload target data sheet/acdc target specif ication 61 v 0.7 preliminary, 2010-03 1.5 pin reliability in overload 1.5.1 introduction when receiving signals from th e external world or higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own io power supply. in order to design cost -optimized high-reliability system s (close to 0 ppm fail-rate in the whole lifetime), some design issues must be taken into account. this document describes these issues. they are relevant on ly for the overloaded input pins/pins set to input of the device/application. there are two types of constr aints for an input pad in overload: vo ltage and current constraints. at 3.3v low vo ltage cmos devices, the voltage constraint s are more critical than the current co nstraints. the reason for this effect is the thin ner gate oxide layer at low-voltage devices. this effect is intrinsic to the gate oxide and can not be avoided. two general cases are discussed in this document: ? full life-time, normal operation, high /room temperature reliability (24000 h) ? limited duration, error case, high/room temperat ure reliability (2400 h) 1.5.1.1 pin classes all tc1782 pins include internal protecti on diodes connected to power supply voltage and to ground. however, the voltage/current ch aracteristics differs in case of different types of pads. there are three classes of gpio p ads, regarding their input characteristics: ? a2 - strong driver pad ? a1, and digital inputs only - low leakage pads ? lvds combo pads generally, the strong driver class has lower protection diode voltage drop than the low leakage class. this means that strong driver pins experience less voltage in overload then the ot her pins. 1.5.1.2 external influences apart from the input current, two other fact ors influence the volt age that will appear on an input pin in overload : the power supply voltage and the die temperature. increasing the power supply volt age directly increases the voltage on all pins in overload. when power supply voltage would increase from nominal 3.3 v to maximal 3.47 v, voltage on all overloaded pins would increase for 0.17 v. when the temperature goes lowe r, the pn-junction voltage goes higher, provided that the current remains consta nt. for the automotive temperature range of -40 o c to +150 o c
tc1782 electrical parameterspin reliability in overload target data sheet/acdc target specif ication 62 v 0.7 preliminary, 2010-03 junction temperature, the volt age variations of up to 0.3 v are possible. on the other hand, gate oxide reliability in creases at lower temperatures . thus, the high temperature case is the worst case, al though at lower temp eratures the voltages are higher. 1.5.1.3 general recommendations the following general recomm endation apply, when designi ng high reliability systems: normal operation case (full lifetime case): 1. use the normal operation instead of overload, whenever possible. 2. use voltage dividers to bring the volt age down to normal operating range. this is recommended for the a1 class pads and the digital input only pads in full lifetime overload. this connection has a property that the pins can go no higher than the divided voltage, inde pendently of the temperature and the power supply variations, if the divided voltage is lower than the nominal supply volt age. in other cases, consult the reliability data as listed in reliability characteristi cs, high temperatures . 3. current limiting with serial resistors only , full lifetime, for a2 class pads gives the reliability data as listed in reliability characteristics, high temperatures . error case (limited duration case): 1. limit the overload current as low as possible. consult the reliability dat a as listed in reliability characteristi cs, high temperatures . additionally: ? when interfacing signals with l ong idle times (inte rrupts, serial cl ocks ...) it is reasonable, whenever possible, to us e the low level as the idle level. ? using power supplies with smal ler static tolerance directly improves the reliability.
tc1782 electrical parameterspin reliability in overload target data sheet/acdc target specif ication 63 v 0.7 preliminary, 2010-03 1.5.2 positive overload 1.5.2.1 reliability at room temperature the reliability data giv en in this document is calculated for one pin of each relevant class. the reliability of n pins is derived by mult iplying the one-pin reliab ility with the number of pins under consideration, of ea ch pad class separately. the high temperature case is the worst case, although the pn-junction voltages at high temperatur es are the lowest. pn junction characteristics the following table gives the pn-juncti on voltage current dependence for room temperature, diff erent pin classes. these pin overload voltag es refer to the nominal power supply of v ddp =3.3v. the maximum values ar e obtained, at v ddp = 3.47 v, by adding 0.17 v to the values above. reliability characteristics, room temperature the following tables give the reliability calculated for sing le pin of each class, room temperature, total life-time 24 000h. the reliability is expre ssed as failure rate in parts per million (ppm), fo r the whole lifetime. note: failure rate for 50% and 10% lifetime exposure to ov erload at room temperature approaches 0. table 31 pn-junction characteristics class 0.2 ma 0.5 ma 1 ma 3 ma lvds 4.0 v 4.05 v 4.15 v 4.35 v fadc / digital input 4.1 v 4.12 v 4.14 v 4.17 v a1 3.95 v 4.06 v 4.1 v 4.15 v a2 3.73 v 3.78 v 3.84 v 4 v table 32 100% lifetime exposure to overload (1 00% duty cycle) class 3.7v 3.8v 3.9v 4.0v 4.1v 4.2v 4.3v fadc / digital input 0 0 0 2e-8 2e-7 3e-6 4e-5 a1 0 0 0 1e-8 1e-7 2e-6 2e-5 a2, lvds 0 0 0 4e-8 4e-7 5e-6 6e-5
tc1782 electrical parameterspin reliability in overload target data sheet/acdc target specif ication 64 v 0.7 preliminary, 2010-03 1.5.2.2 reliability at high temperatures the reliability data giv en in this document is calculated for one pin of each relevant class. the reliability of n pins is derived by mult iplying the one-pin reliab ility with the number of pins under consideration, of each pad class separately. the high temper ature case is the worst case, although the pn -junction voltages at high te mperatures are the lowest. pn junction characteristics the following table gives the pn-junction voltage cu rrent dependence for 125 o c, different pin classes. these pin overload volt ages refer to the nomi nal power supply of v ddp =3.3v. the maximum values ar e obtained, at v ddp = 3.47v, by adding 0.17v to the values above. reliability characterist ics, high temperatures the following tables give the reliability calculated for a si ngle pin of each pad class, high temperature, total li fe-time 24000h at 125 o c junction temperatur e. the reliability is expressed as failure rate in parts per million (ppm), for the whole lifetime. table 33 pn-junction characteristics class 0.2 ma 0.5 ma 1 ma 3 ma lvds 3.93 v 4 v 4.05 v 4.3 v digital only 3.93 v 4 v 4.05 v 4.25 v fadc 3.93 v 4 v 4.05 v 4.1 v a1 3.85 v 3.95 v 4 v 4.07 v a2 3.66v 3.72 v 3.78 v 3.9 v table 34 100% lifetime exposure to overload (1 00% duty cycle) class 3.7v 3.8v 3.9v 4.0v 4.1v 4.2v 4.3v fadc / digital input 0.0001 0.0012 0.016 0.21 2.7 35 460 a1 0.00005 0.0006 0.008 0.1 1.3 17 220 a2, lvds 0.00014 0.0018 0.024 0.31 4 53 690 table 35 50% lifetime exposure to overload (50% duty cycle) class 3.7 v 3.8 v 3.9 v 4.0 v 4.1 v 4.2 v 4.3 v fadc / digital input 0.00001 0.00012 0.0015 0.02 0.26 3.4 44 a1 0.000005 0.00006 0.0007 0.01 0.12 1.6 21 a2, lvds 0.000013 0.00017 0.0022 0.03 0.38 5 65
tc1782 electrical parameterspin reliability in overload target data sheet/acdc target specif ication 65 v 0.7 preliminary, 2010-03 1.5.2.3 reliability calculation method for each application a list of pins /overload conditions must be generated. first, currents per pin class, duration and number of pins are defined. for example: then, from the pn-junction characteristics t able (for high temperature), the voltages are filled in. then, from the reliab ility tables for 125 o c, the appropriat e reliability per pi n is filled in. table 36 10% lifetime exposure to over load (in case of an external error) class 3.7 v 3.8 v 3.9 v 4.0 v 4.1 v 4.2 v 4.3 v fadc / digital input 4e-10 5e-9 6e-8 0.0001 0.0011 0.014 0.2 a1 2e-10 3e-9 3e-8 0.000 04 0.0005 0.007 0.1 a2, lvds 5e-10 7e-9 1e-5 0.00012 0.0016 0.02 0.3 table 37 step 1 class current [ma] voltage [v] duration [lifetime%] reliability [ppm] no. of pins lvds 0,5 50% 4 fadc 3 10% 3 a1 1 50% 5 a2 1 50% 10 table 38 step 2 class current [ma] voltage [v] duration [lifetime%] reliability [ppm] no. of pins lvds 0.5 450% 4 fadc 3 4.1 10% 3 a1 1 450% 5 a2 1 3.78 50% 10 table 39 step 3 class current [ma] voltage [v] duration [lifetime%] reliability [ppm] no. of pins lvds 0.5 4 50% 0,03 4 fadc 34.110% 0,0011 3
tc1782 electrical parameterspin reliability in overload target data sheet/acdc target specif ication 66 v 0.7 preliminary, 2010-03 last step 4 consists of multip lying the reliability with the corresponding number of pins and summing th e results. in this case: reliability [ppm] = 0.00017*10+0.01*5+0.03*4 = = 0.0017 +0.05 + 0. 12 = ca. 0.17 ppm this calculation is done for 3.3 v nominal power supply, at 125 o c. if the upper maximum power supply voltage of 3,47 v is taken into account, then 0.17 v should be added to the overload voltages in step 2. the corresponding number would not correspond to the statistical reality, because most of the po wer supplies do not supply the maximum upper limit voltage (see gene ral recommendations - section 1.5.1.3 ). figure 20 graphical representatio n of the calculation process the figure 20 illustrates the concept behind the calcul ation. starting point is the overload current, and the ending point is the ppm rate. the total ov erload voltage on a pin is a sum of the port supply voltage and t he voltage of the protec tion diode in overload. a1 14 50% 0,01 5 a2 13.7850% 0,00017 10 table 39 step 3 class current [ma] voltage [v] duration [lifetime%] reliability [ppm] no. of pins 3.7v 0v vin [v] ppm i [ma] 0.5 1 2 3 1.5 2.5 u [v] 0.4 0.5 0.6 0.7 0.8 0.9 3.8 3.9 4.0 4.1 4.2 4.3 1 0.1 0.01 0.001 125 o c 50% duty cycle a2 pads others tj=125 o c start end overload current 0.0001 <125 o c a2 pads 3.3v 5% + - v ddp =
tc1782 electrical parameterspin reliability in overload target data sheet/acdc target specif ication 67 v 0.7 preliminary, 2010-03 the figure 20 also shows that exceeding the 3.7 v on a pin leads to the necessity of calculating the failure rate in ppm, at high temperatur e and whole lifet ime (50% duty cycle assumed). the figure 20 does not intend to describe accurately the physical laws and is not to be used as a ca lculation tool but only as an illustration. calculations must be performed according to the described four steps procedure. 1.5.3 negative overload the negative overload appears when the voltage on an input pin goes below the v ss . the stress on some gox surfac es is determined by the difference between the v ddp power supply voltage and the voltage at the input pi n. for example, if v ddp = 3.3 v, and v in = -0.7 v, than the internal stre ssing voltage is equal to 4 v. generally, this kind of stress influences fewer internal stru ctures than the po sitive overload. 1.5.3.1 reliability at high temperatures the reliability data given in th is document is calculated for one pin of each relevant class. the reliability of n pins is derived by mult iplying the one-pin reliab ility with the number of pins under considerat ion, of each pad class separatel y. the high temp erature case is the worst case, although the pn -junction voltages at high te mperatures are the lowest. pn junction characteristics the following table gives the pn-junction voltage cu rrent dependence for 125 o c, different pin classes. adding 3.3 v to the absolute values from the table abov e gives the stressing voltage: table 40 pn-junction characteristics class -0.2 ma -0.5 ma -1 ma -3 ma lvds / digital input -0.31 v -0.35 v -0.4 v -0.48 v fadc -0.31 v -0.39 v -0.4 v -0.48 v a1 -0.52 v -0.61 v -0.66 v -0.73 v a2 -0.29 v -0.34 v -0.38 v -0.46 v table 41 equivalent stressi ng voltage (3.3 v - u pn ) class -0.2 ma -0.5 ma -1 ma -3 ma lvds / digital input 3.61 v 3.65 v 3.7 v 3.78 v fadc 3.91 v 3.96 v 4.0 v 4.05 v a1 3.82 v 3.91 v 3.96 v 4.03 v a2 3.59 v 3.64 v 3.68 v 3.76 v
tc1782 electrical parameterspin reliability in overload target data sheet/acdc target specif ication 68 v 0.7 preliminary, 2010-03 these pin overload voltag es refer to the nominal power supply of v ddp =3.3v. the maximum values ar e obtained, at v ddp = 3.47 v, by adding 0.17 v to the values above.
tc1782 electrical parameterspin reliability in overload target data sheet/acdc target specif ication 69 v 0.7 preliminary, 2010-03 reliability characterist ics, high temperatures the following tables give the reliability calc ulated for a single pin of each pad class, high temperature, total li fe-time 24000h at 125 o c junction temperatur e. the reliability is expressed as failure rate in parts per million (ppm), for the whole lifetim e. the data is related to the negative overload condit ion, and equivalent stressing voltage. the reliability calculation met hod for the negative ov erload is the same as for the positive overload. table 42 stress voltage vs. negative overload voltage for vddp=3.3v overload -0.4 v -0.5 v -0.6 v -0.7 v -0.8 v -0.9 v -1.0 v stress 3.7v 3.8v 3.9v 4.0v 4.1v 4.2v 4.3v table 43 100% lifetime exposure to overload (1 00% duty cycle) class 3.7v 3.8v 3.9v 4.0v 4.1v 4.2v 4.3v digital input ? ? ? ? 0.0003 0.002 0.009 fadc ??????? a1 ? ? ? 0.0002 0.0007 0.004 0.02 a2, lvds ? ? 0.0002 0.0008 0.005 0.03 0.2 table 44 50% lifetime exposure to overload (50% duty cycle) class 3.7v 3.8v 3.9v 4.0v 4.1v 4.2v 4.3v digital input ? ? ? ? ? 0.0004 0.002 fadc ? ? ??? ? ? a1 ? ? ? ? 0.0002 0.0009 0.006 a2, lvds ? ? ? 0.0002 0.001 0.007 0.04 table 45 10% lifetime exposure to over load (in case of an external error) class 3.7 v 3.8 v 3.9 v 4.0 v 4.1 v 4.2 v 4.3 v digital input ? ? ? ? ? ? 0.0001 fadc ??????? a1 ? ? ? ? ? ? 0.0002 a2, lvds ? ? ? ? ? 0.0003 0.002
tc1782 electrical parameterspin reliability in overload target data sheet/acdc target specif ication 70 v 0.7 preliminary, 2010-03 1.5.4 fadc input buffer reliability the fadc input buffer is designed to operate within the normal o perating conditions with input signals in 3.3 v range. overload condition can occur in the fadc if: ? a channel connected to 3. 3 v input pad receives a voltage higher than the v ddmf (3.3 v) supply voltage ? on an overlayed channel t he fadc is enabled and the input sig nal is higher than v ddmf overlayed fadc pins share the 5 v esd pr otection with the adc and non-overlayed fadc pins have their dedic ated 3.3 v esd protection. all fadc input stages (double transmission gates) ar e protected with diodes against overvoltage. the diodes limit the input voltage for all fadc inputs to 4.3 v. note: if an overload fadc channel is se lected with a si gnal higher than v ddmf +0.7 v the protection diode will cl amp the input voltage to th is level and cause additional leackage for the adc input signal. this will increase the error of the adc measurement. 1.5.5 lvds / cmos combo pad reliability the lvds / cmos combo pads ar e complex pads with relative ly large stressed area, comparable to the stressed area of the a2 pads on one side, and ui characteristics of the esd elements resulting in higher over-vol tages on the other si de. that makes them somewhat more sensitive to overload than the othe r digital pads. for the exact numbers, use the given values in the tables and the descri bed calculation method.
tc1782 electrical parameterspin reliability in overload target data sheet/acdc target specif ication 71 v 0.7 preliminary, 2010-03 1.5.6 overload electrical parameters note: under the following overload co nditions at the digital gpio pins: -1 ma www.infineon.com published by infineon technologies ag

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